Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-06-14
2005-06-14
Iqbal, Nadeem (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S030000
Reexamination Certificate
active
06907548
ABSTRACT:
A test circuit disposed between a common bus and the cores of a multi-core computer permits post-silicon validation in the form of controlled stress testing of the system. The test circuit may block data requests from one or more selected cores and issue test data requests into the system instead, resulting in a more controllable test environment. In one embodiment, the test circuit is programmed and monitored from an external device through an integrated test port.
REFERENCES:
patent: 5596734 (1997-01-01), Ferra
patent: 6134675 (2000-10-01), Raina
patent: 6496880 (2002-12-01), Ma et al.
patent: 6550020 (2003-04-01), Floyd et al.
patent: 6732311 (2004-05-01), Fischer et al.
patent: 2002/0083387 (2002-06-01), Miner et al.
patent: 2003/0005380 (2003-01-01), Nguyen et al.
patent: 2003/0126531 (2003-07-01), Tu et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Iqbal Nadeem
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