Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-06-14
2011-10-11
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S200000
Reexamination Certificate
active
08037378
ABSTRACT:
A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key or command as the next command received, the test mode is disabled. If the appropriate key is received, the test mode is continued to be enabled until it is expressly disabled by the user.
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Britt Cynthia
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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