Automatic test entry termination in a memory device

Details Automatic test entry termination in a memory device Automatic test entry termination in a memory device

2006-12-26

2006-12-26

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S200000

Reexamination Certificate

active

07155644

ABSTRACT:
A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key or command as the next command received, the test mode is disabled. If the appropriate key is received, the test mode is continued to be enabled until it is expressly disabled by the user.

REFERENCES:
patent: 5394403 (1995-02-01), Klein
patent: 5905690 (1999-05-01), Sakurai
patent: 5950145 (1999-09-01), Roohparvar
patent: 6028798 (2000-02-01), Roohparvar
patent: 6108798 (2000-08-01), Heidel
patent: 6353563 (2002-03-01), Hii
patent: 6452848 (2002-09-01), Obremski

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