Automatic test circuit for a semiconductor memory device capable

Details Automatic test circuit for a semiconductor memory device capable Automatic test circuit for a semiconductor memory device capable

1995-11-07

1996-11-26

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

365193, 365233, 36523008, 365236, G11C 2900

Patent

active

055792715

ABSTRACT:
An automatic test circuit for automatically testing the operation of a semiconductor memory device to check whether it is normal or abnormal. The automatic test circuit comprises a test command signal generation stage for generating a test command signal in response to an external row address strobe signal, an external column address strobe signal, an external write signal and an external read signal, a row address signal generation stage for generating an internal row address strobe signal and a row address signal in response to the external row address strobe signal and the test command signal from the test command signal generation stage, and a column address signal generation stage for generating an internal column address strobe signal and a column address signal in response to the internal row address strobe signal from the row address signal generation stage and the test command signal from the test command signal generation stage.

REFERENCES:
patent: 5204837 (1993-04-01), Suwa et al.

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