Automatic synthesizing method for logic circuits

Details Automatic synthesizing method for logic circuits Automatic synthesizing method for logic circuits

1998-04-06

2000-08-01

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 2, 716 7, 716 17, G06F 1750

Patent

active

060960922

ABSTRACT:
Logic circuits are experimentally automatically synthesized, and a representative line length of each fanout number is estimated on the basis of a net list resulting from the synthesis. The representative line length corresponds to a length of a line positioned at a center when plural lines are aligned in the order of their lengths (namely, a median line length WLmed(fn)). Furthermore, a standard deviation .sigma.med(fn) and a probability coefficient K(fn) of the deviation are calculated with regard to each fanout number on the basis of the net list. Then, a defined line length WL(fn) of each fanout number fn is calculated by using an expression, WL(fn) =WLmed(fn)+K(fn).multidot..sigma.med(fn). At this point, when there is a demand for design of an LSI having a high operation speed, the probability coefficient K(fn) is set at a small value, and when there is a demand for design of an LSI completed in a short period of time, the probability coefficient K(fn) is set at a large value. Then, by using a virtual wiring model including the defined line length WL(fn), the logic circuits are automatically synthesized, and a net list resulting from the synthesis is used for generating a layout of the logic circuits.

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