Automatic shutoff for memory load device during write operation

Details Automatic shutoff for memory load device during write operation Automatic shutoff for memory load device during write operation

1991-08-14

1993-07-06

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

36518908, 365227, G11C 700

Patent

active

052260070

ABSTRACT:
The present invention is directed to semiconductor memories which can operate at faster speeds with reduced power dissipation. In a preferred embodiment, load devices of a memory array, such as a SRAM, are automatically turned off during a write operation in response to detected bit line activity. Accordingly, considerable power is saved while minimizing memory architecture and the potential for power surges during a write enable.

REFERENCES:
patent: 4665507 (1987-05-01), Gondou et al.
patent: 4933905 (1990-06-01), Ootani

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