Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2005-12-06
2008-10-28
Bragdon, Reginald G. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S171000, C711S172000
Reexamination Certificate
active
07444491
ABSTRACT:
Embodiments of the present invention recite a method and system for allocating memory resources. In one embodiment, a control component coupled with a memory device determines that a data buffer adjacent to a boundary of a first FIFO queue does not contain current data. The control component also determines that a second data buffer of a second FIFO queue adjacent to the boundary does not contain current data. The control component then automatically shifts the boundary to include the second data buffer in the first FIFO queue.
REFERENCES:
patent: 6678813 (2004-01-01), Le
patent: 7176928 (2007-02-01), Sendrovitz
Bragdon Reginald G.
Dinh Ngoc V
nVIDIA Corporation
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