Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-07-16
2003-07-01
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06587997
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the gathering of resistance and capacitance data from integrated circuit designs from multiple foundries as input to computer aided design tools, which can provide circuit analyses. These analyses include coupling noise, electromagnetic interference generation, power dissipation, and resistive voltage drop. More particularly, this invention relates to the automatic generation of resistive/capacitive technology data files, which are converted to formats usable by computer aided design analysis programs from a generic technology file.
2. Description of Related Art
Today, integrated circuit designers must use design automation tools for analysis of semiconductor circuits. The various analyses
170
include noise coupling analysis, resistive voltage drop calculation, determining electromagnetic interference effects, circuit delay calculation, and power dissipation analysis. These analysis tools come from different design automation tool providers. As shown in
FIG. 1
, a typical circuit designer may deal with multiple foundries
100
,
110
,
120
to fabricate their designs. Each foundry
100
,
110
,
120
provides the process parameters that determine the resistivity and dielectric contants of the materials employed in fabricating an integrated circuit in the semiconductor process. The foundries may differ in their minimum possible line widths or in the type of dielectric material used to make capacitors for example. In addition, the circuit designer utilizes computer aided design analysis applications or tools
130
,
140
,
150
,
160
from different vendors. It is the designer's responsibility to supply the required input information, such as resistivity, dielectric, and other physical properties) from the semiconductor foundries to the computer aided analysis tools. The results from the analysis tools are only accurate and useful if the required material properties are accurate and correct. Typically, the circuit designer has to manually prepare technology data files which gather information such as the resistivity, dielectric constants, wiring lengths and widths, oxide thickness from the foundries
100
,
110
,
120
and provide this information in the varied formats required by the different computer aided analysis tools providers. As shown in
FIG. 1
, four different Technology Data Files (TDF)
125
,
135
,
145
,
155
may be required per chip coming from a single foundry. If the chip is fabricated at two foundries, the number of TDF files the circuit designer must generate would be eight. If the chip is fabricated at three foundries, the number of TDF files the designer must generate would be twelve, as shown.
Referring now to
FIGS. 2
a
,
2
b
, and
2
c
for a discussion of the information contained within a technology description file (TDF)
400
necessary for calculation of capacitance and resistance of semiconductor structures that form integrated circuits.
FIG. 2
a
illustrates a header structure for a TDF
400
. The header structure provides a technology name describing the process to be used within the foundry
100
,
110
,
120
described by the technology data file
400
. The header has a label for the tolerance level or CASE of the detail dimensions of the technology described. The tolerance level or CASE will either be “normal,” “best”, or “Worst” case. The header further contains a title detailing more information about the process of the foundry
100
,
110
,
120
. The header also contains a revision code and data to chronicle changes in the TDF
400
. The intended modeling tool is described. In this example SPICE, a circuit level simulation program well known in the art, is named as the target modeling tool. The SPICE circuit model description file is the source of the TDF. The name of the author(s) of the TDF
400
identifies the person responsible for creating and revising the TDF
400
.
FIG. 2
b
describes the contents of the TDF
400
for the dielectric insulation layers used to isolate conductive layers used in forming and interconnecting the electronic components of the integrated circuit. The statement demarcated by the double backward slash marks (//) indicate comments describing the fields of the TDF
400
. The text //type describes the type of material specified. The dielectric material is denoted with a D, a conductor is denoted with a C, the diffusion layers are noted with an F, and a passivation layer is denoted with a P.
The dielectric constant (die-c) is itemized for each type of insulating material by layer that is used. The thickness is described, as is the variation in the thickness as a percentage of the thickness.
The diffusion layers are described giving the depth within the semiconductor substrate for the diffusion, the minimum thickness of the diffusion, the minimum dimensions (MinW) of the diffusion, the minimum spacing (MinS) between diffusions, the resistivity of the diffusion material, and a bias or difference between the designed or drawn dimensions and the actual fabricated dimensions.
FIG. 2
c
illustrates the TDF
400
entries for conductors placed on a semiconductor substrate to interconnect the electronic devices of the integrated circuit and to form the gate structures of field effect transistors (FET's) of the integrated circuit. The specification of the TDF
400
for conductors include the height above the substrate for each conductor, the thickness of the conductors, the minimum dimensions (MinW) of the conductor, the minimum spacing between conductors (MinS), the resistivity of the conductors, a bias factor for the difference between the designed or drawn dimensions and the actual dimensions, the overlaying dielectric layer (ABOVE), and the variations as a percentage of the thickness and width of the conductor (
3
d
1
,
3
d
2
).
The description of the via contacts or interlayer connection for conductors includes the resistance (ohm/ct) for each via contact, the width and length of the via contact, the name of the lower conductor (low-m), and the name of the upper conductor (upper-m).
As is understood by a person skilled in the art, the TDF
400
as shown provide sufficient information for calculating the resistance of the conductive layers and the diffusions, and the capacitance formed between any of the conductive layers. Further, the TDF
400
, as shown, is used as a source document and is translated to the format acceptable as technology files for commercially available computer aided design programs
“Verification of Circuits Described in VHDL Through Extraction of Design Intent,” Hoskote et al, Proceedings of the Seventh International Conference on VLSI Design, IEEE, January, 1994, pp. 417-420, describes a verification framework to verify VHDL designs from the scheduled behavioral level down to the gate level by capturing the design intent, on the basis of a formal semantics, in a form appropriate for input to the verifier.
“Efficient Net Extraction for Restricted Orientation Designs [VLSI Layout],” Lopez et al., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Sept. 1996 Vol. 15 Issue: 9 ISSN: 0278-0070, pp. 1151-1159 describes an algorithm to extract a physical net description based on the intersections of connections within a net.
U.S. Pat. No. 6,009,252 (Lipton) teaches a layout versus schematic(LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to generate color symmetric matrices corresponding to respective child cells in the integrated circuit schematic.
U.S. Pat. No. 5,452,224 (Smith, Jr. et al.) describes a method for computing parasitic capacitances between multiple electrical conductors within an electric circuit. The parasitic capacitances associated with the conductors of each window are computed, and the results for the various windows combined into a matrix of parasitic capacitances for the overall circuit.
U.S. Pat. No. 5,706,206 (Hammer, et al.) describes a method
Chen Steven
Hou Cliff
Ackerman Stephen B.
Bowers Brandon
Knowles Billy
Saile George O.
Siek Vuthe
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