Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-05-30
2006-05-30
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C327S198000
Reexamination Certificate
active
07055064
ABSTRACT:
A circuit for automatically resetting a central processing unit (CPU) is provided. The circuit includes a detector and a reset signal generator. The detector is electrically connected to the CPU for receiving a specified signal from the CPU, and the detector sends out a triggering signal when the specified signal is not received for a predetermined period of time. The reset signal generator is electrically connected to the detector for generating a reset signal in response to the triggering signal. A chipset with a reset completion indication function is also provided. The chipset includes a plurality of functional circuits and a calculating and recording device.
REFERENCES:
patent: 4803682 (1989-02-01), Hara et al.
patent: 5594865 (1997-01-01), Saitoh
patent: 6070248 (2000-05-01), Yu et al.
patent: 6085319 (2000-07-01), Uemura
patent: 6134655 (2000-10-01), Davis
patent: 6788156 (2004-09-01), Tam et al.
patent: 6883123 (2005-04-01), Hashimoto et al.
patent: 2002/0003442 (2002-01-01), Kuboshima et al.
Beausoliel Robert
Madson & Austin
McCarthy Christopher
Via Technologies Inc.
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