Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2000-08-15
2002-06-11
Thai, Tuan V. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S105000, C711S154000, C711S167000, C711S202000, C365S230010, C365S230050, C714S048000
Reexamination Certificate
active
06405297
ABSTRACT:
THE FIELD OF THE INVENTION
The present invention relates to semiconductor memory integrated circuits and, more particularly, to serial input and output operations in multiple port random access memory devices such as video RAMs.
BACKGROUND OF THE INVENTION
A video RAM (VRAM) is a dynamic random access memory (DRAM) having a serial input/output I/O port coupled to a serial access memory (SAM). The SAM permits a block of stored data to be rapidly accessed, while the normal access function of the DRAM is also occurring. The information stored in the SAM is normally obtained from, or input into, a primary memory on the VRAM. The primary memory is typically configured as a DRAM array and is accessed according to normal DRAM protocols.
Information can be written into the VRAM at DRAM address speeds and output through the serial access port, or vice versa. This serial writing and access capability is convenient for video applications because some address sequences, such as pixels in a raster scan, are predetermined.
The McLaury U.S. Pat. No. 5,325,502 entitled PIPELINED SAM REGISTER SERIAL OUTPUF, is commonly assigned to Micron Technology, Inc., the assignee of the present application, and is incorporated herein by reference. The U.S. Pat. No. 5,325,502 patent describes a VRAM having a faster serial read operation by pipelining the serial read operation. The pipelined serial read operation performs many of the necessary serial read operations steps concurrently, rather than performing all of the steps serially as was done previously. In particular, the preferred embodiment described in the U.S. Pat. No. 5,325,502 patent pipelines the serial read operation by partitioning the serial read operation to form a sensing operation, a counter operation, and an output operation wherein all three operations proceed concurrently.
The U.S. Pat. No. 5,325,502 patent describes a pipelined SAM architecture, but does not address the situation where a split read transfer operation is performed on SAM split boundry. A need exists for a pipelined SAM architecture VRAM, such as described in the U.S. Pat. No. 5,325,502 patent, which performs a split read transfer operation which meets normal, non-pipelined SAM specifications.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit responsive to command signals and a tap address signal for providing an output signal. The integrated circuit includes a memory array storing data, and a serial access register having multiple cells. The serial access register is divided into a first portion and a second portion. Transfer circuitry transfers selected data from the memory array into the first portion of the serial access register. A tap address latch stores the tap address signal. Pointing circuitry responds to the stored tap address signal to assign values to an internal address signal by starting at a tap address signal value. Reading circuitry reads cells in the second portion of the serial access register identified by the internal address signal, and provides the output signal corresponding to the read cells. Timing circuitry controls the transfer circuitry, the pointing circuitry, and the reading circuity so that the reading circuitry provides the output signal corresponding to a first cell in the second portion while: 1) the reading circuitry reads a second cell in the second portion; 2) the pointing circuitry assigns a value to the address signal corresponding to a third cell in the second portion; and 3) the transfer circuitry transfers selected data from the memory array into the first portion. A controller responds to the command signals and the internal address signal reaching a stop address boundary in the second portion to cause the pointing circuitry to re-start the value of the internal address signal at a tap address value in the first portion. The controller responds to the command signals up to the stop address boundary to cause the internal address to re-start at the tap address value in the first portion.
In a preferred embodiment of the present invention the controller includes a boundary recognition sensor providing a boundary detect signal indicating that the data bit stored in the cell being read by the reading circuitry corresponds to the stop address boundary. A boundary latch preferably stores the state of the boundary detect signal in response to serial clock signal received by the integrated circuit. Alternatively, the controller includes a boundary+1 recognition sensor providing a boundary+1 detect signal indicating that the data bit stored in the cell being read by the reading circuitry is one past the stop address boundary.
The controller preferably includes circuitry generating a tap load signal to cause the internal address to re-start at the tap address value in the first portion. The tap load signal is generated when the data bit stored in the cell being read by the reading circuitry is one past the stop address boundary and the command signals indicate an initiation of a split read transfer operation to direct the timing circuitry to control the transfer circuitry to transfer the selected data into the first portion of the serial access register while the reading circuitry reads data from the second portion. The tap load signal is preferably generated in response to a state of one of the command signals which indicates that valid data is the tap address latch. In one embodiment of the present invention, the one command signal is a column address strobe signal used to strobe a state of the tap address signal into the tap address latch.
The stop address boundary is optionally programmable. In addition, more than one stop address boundary can be programmed for each portion of the serial access register.
REFERENCES:
patent: 4819213 (1989-04-01), Yamaguchi et al.
patent: 4839856 (1989-06-01), Tanaka
patent: 4891795 (1990-01-01), Pinkham et al.
patent: 4989181 (1991-01-01), Harada
patent: 5042014 (1991-08-01), Pinkham et al.
patent: 5097447 (1992-03-01), Ogawa et al.
patent: 5179372 (1993-01-01), West et al.
patent: 5198999 (1993-03-01), Abe et al.
patent: 5200925 (1993-04-01), Morooka
patent: 5206831 (1993-04-01), Wakamatsu
patent: 5289413 (1994-02-01), Tsuchida et al.
patent: 5305278 (1994-04-01), Inoue et al.
patent: 5313431 (1994-05-01), Uruma et al.
patent: 5325329 (1994-06-01), Inoue et al.
patent: 5325332 (1994-06-01), Tagaya
patent: 5325502 (1994-06-01), McLaury
patent: 5379263 (1995-01-01), Ogawa et al.
patent: 5450364 (1995-09-01), Stephens, Jr. et al.
patent: 5678017 (1997-10-01), Morgan
Drake E. E.
Schwegman Lundberg Woessner & Kluth P.A.
Thai Tuan V.
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