Automatic reference voltage regulation in a memory device

Details Automatic reference voltage regulation in a memory device Automatic reference voltage regulation in a memory device

2002-11-18

2004-05-18

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S189050, C365S189070

Reexamination Certificate

active

06738298

ABSTRACT:

BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates generally to reference voltage adjustments and particularly to adjustment of a reference voltage in a memory device.
II. Description of the Related Art
Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. There are currently many different types of memory.
One type is random access memory (RAM). This is typically used as the main memory in a computer system. RAM refers to memory that can be both written to and read from. This is in contrast to read only memory (ROM) that permits data to only be read. Most RAM is volatile meaning that it requires a steady flow of power to maintain its contents. When power is turned removed, the data in RAM is lost.
An electrically erasable programmable read-only memory (EEPROM) is a special type of non-volatile ROM that can be erased a byte at a time by exposing it to an electrical charge. EEPROMs comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of a charge on the floating gates. The charge is transported to or removed from the floating gates by programming and erase operations, respectively.
A flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory device comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be randomly programmed by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
Some EEPROM and flash memory devices require an internal reference voltage that is used to determine when certain cells are programmed. Each cell is coupled through a bit line (also known as a column) to a sense amplifier. When the particular cell is accessed through the row and column signals, that cell is coupled to one input of the sense amplifier. The other input of the sense amplifier is connected to the reference voltage (V
ref
). The difference between the two voltages determines if the cell has been programmed. V
ref
, therefore; must be an accurate voltage since the difference may come down to tenths of volts.
A memory device etched into a die may have slightly different properties than the same circuit etched into second die. V
ref
on each of these two dies may differ by a couple tenths of volts. In order to maintain consistent results and high quality, these voltages need to be made consistent.
One way that has been used to adjust V
ref
is with a trim adjustment circuit. A typical prior art trim adjustment circuit
100
is illustrated in FIG.
1
. This circuit
100
is included on the die with the memory circuitry.
The trim adjustment circuit
100
is connected to an external test device through the integrated circuit's data bus
101
. The test device transmits data over the bus
101
to instruct the circuit
100
to change the resistance of the trim circuit
122
in order to change the reference voltage generated by the V
ref
voltage circuit
125
.
The test device sends four bits of data over the bus
101
that is converted to complementary data prior to being input to the circuit
100
. This data and their complementary signals are shown as FL
0
, FL
0
*, FL
1
, FL
1
*, FL
2
, FL
2
*, FL
3
, and FL
3
*. The data is input through fuse latches
103
-
106
to a fuse decoder
120
. The fuse decoder
120
decodes the data to correspond to one of sixteen decode lines (i.e., d
0
-d
15
) connecting the decoder
120
to the trim circuit
122
.
The decode lines select one of sixteen possible resistor combinations in the trim circuit
122
that is connected to the reference voltage circuit
125
. The output voltage from the reference voltage circuit
125
is connected to the external test device in order to measure the V
ref
that is generated with a particular combination of resistors in the trim circuit
122
.
One problem with the prior art device of
FIG. 1
is that the test device has to load a data value, measure the generated reference voltage, and determine if that voltage is correct. This may have to be repeated for all sixteen possible data combinations (i.e., 0000-1111) in order to find the proper combination of resistors to generate the desired V
ref
. These steps have to be repeated for each individual die in a serial fashion in order to achieve maximum V
ref
accuracy. Such time consuming procedures cost the integrated circuit manufacturer valuable production time. There is a resulting need in the art for a quicker way to adjust an integrated circuit's reference voltage.
SUMMARY
The present invention encompasses a reference voltage adjustment circuit comprising a counter circuit that generates a count signal. A decoder circuit is coupled to the counter circuit. The decoder circuit decodes the count signal to generate a resistance selection signal. The resistance selection signal is input to a resistor network that generates a resistance value in response to the resistance selection signal. The resistance value is coupled to a reference voltage circuit that generates an updated reference voltage in response to the resistance value.
In one embodiment, the updated reference voltage is compared to a reference voltage provided from an external source. If the two voltages are substantially equal, the counter circuit is disabled.


REFERENCES:
patent: 6147908 (2000-11-01), Abugharbieh
patent: 6449197 (2002-09-01), Hiraki et al.
patent: 6459649 (2002-10-01), Krause
patent: 6496436 (2002-12-01), Naji

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