Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-02-10
2002-01-15
Iqbal, Nadeem (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C327S020000
Reexamination Certificate
active
06339833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to clock/data recovery systems and more particularly to an apparatus and method for applying digital techniques to initiate a recovery process upon detecting the loss of a signal.
2. Description of the Related Art
Data transmission systems sometimes incorporate accurate and stable delay elements to generate predetermined width pulses, clock synchronization, clock multiplication, and clock/data recovery. In systems that serially transmit and receive data, clock information is generally embedded in the data stream to provide correct timing for data recovery, because there are no separate lines or channels to independently carry the clock signal to the receiver. Clock frequency recovery and phase alignment with the data are typically performed before the received data can be recovered and deserialized.
Traditionally, a Phase Locked Loop (PLL) circuit is employed to recover the clock frequency and align the data with the clock phase. A PLL circuit is a type of circuit that incorporates a Voltage Controlled Oscillator (VCO) whose frequency is continuously adjusted in response to the frequency of the incoming data. Modern data communication systems generally transmit and receive data in digital form, and accordingly implement the PLL in a digital form. Various examples of these systems are disclosed in U.S. Pat. No. 5,457,719; 5,349,612; 5,400,370; 5,367,542; 5,451,894; and 5,264,745. Digital PPL circuits typically employ an adjustable bias voltage, or current, to adjust the delay value of a delay unit in a ring oscillator in order to achieve frequency tuning (or to adjust the phase to match that) of the incoming data. Digital PLL circuits use digital logic for phase detection, filtering, and (at times) the ring oscillator. However, such techniques must be specifically designed to accommodate particular data or coding formats, jitter tolerance, or operational frequencies.
In purely digital approaches to clock and data recovery, the phase offset information is stored in a digital format as a code. The code is stored and constantly updated in specially designed register circuits in order to reflect the phase difference as a function of time. In practice however, the incoming serial data is often contaminated with various types of noises that result in timing or phase jitter. Consequently, the edges (i.e., the transitions) in the data stream do not always arrive at precisely the same time. Rather, the edges arrive at a different (either early or late) times, causing the timing noises (i.e., jitter).
There are several drawbacks to the use of traditional PLL circuits for clock and data recovery. In analog PLL circuits, incorrect phase errors are detected due to excessive noise and adjustments are continually attempted even if the VCO frequency is at the same as, or very close to, the data frequency. PLLs can be designed to reduce the effect of jitter sources in the high frequency range by employing complex low pass filters. However, such filtering often introduces other problems. The control voltage to the VCO is very susceptible to internally generated switching noise, and such susceptibility increases as the operating frequency increases. Furthermore, low pass filters employ large valued components such as capacitors and resistors, hence resulting in increased manufacturing costs when implemented as monolithic integrated circuits.
Digitally implemented PLL circuits tend to be less sensitive to noise than analog PLL circuits under very noisy power supply conditions. However, digital PLL circuits are often subject to a “lock up” condition. Under such lock up conditions, the system enters an undefined state wherein the stored information is either lost or “locked” and, consequently, unretrievable. This is because unlike analog PLL circuits, where there is always a stored bias voltage value (regardless of changes in the power supply voltage), a digital system is typically unable to recover from unwanted states resulting from a power surge unless a full or partial reset operation is performed.
Regardless of the technique implemented (i.e., digital or analog), the recovered clock signal is subsequently used as the receive system clock to get data out of a first-in first-out (FIFO) buffer, or similar type of queue. The host receiving the data stream is thus capable of retrieving the data in the buffer without losing any bits. However, when the clock signal is lost, the recovery process stops. In digital systems, such interruptions correspond to lock up conditions. When an interruption is detected, the host must reset the system, which in a communication network requires shutting down and restarting the link.
According to one approach to digital data recovery, various digital “pointers” are used to indicate the delay calibration status and the phase difference between the local clock and the remote clock which is used to send the data over the serial link. The pointers are constantly adjusted based on variations in temperature, supply voltage, and data phase and frequency. Compared to traditional synchronous digital circuits, these adjustment operations are further complicated by the fact that they relate to two asynchronous clock sources, with one being the local clock and the other being the clock recovered from the data. When a power supply surge occurs, there is a possibility that one of the “pointers” can get lost, and subsequently, the recovered clock signal gets lost. User software “watch dog” functions have previously been used for detecting such losses in order to ensure reliability and automatic recovery from unexpected events. However, in an integrated chip or system, software monitoring systems used by the user can only do a system-wide or chip-wide reset, hence requiring shutting down and restarting the link.
Accordingly, a primary disadvantage associated with current digital methods of recovering asynchronous signals, such as a clock signal, and data from a serially transmitted data stream is the inability to detect and automatically recover from a loss of the recovered clock signal.
DISCLOSURE OF THE INVENTION
There is a need for an arrangement for detecting a loss of asynchronous signals associated with serially transmitted data streams, and initiating a graceful recovery upon detecting the loss of the asynchronous signals.
These and other needs are addressed by the present invention, wherein an input signal that is asyncrhonous to the system clock, but very close in frequency, is monitored, and a reset signal synchronous to the system clock is generated to initiate a recovery process upon detecting the loss of the input signal.
In accordance with one aspect of the invention, an apparatus for initiating automatic recovery from a signal loss comprises a frequency division circuit, an input detection circuit, and a recovery circuit. The frequency division circuit receives a system clock signal, and outputs at least one output signal that has a lower frequency than the system clock signal. The input detection circuit receives an asynchronous input signal and outputs a first output signal. The first output signal indicates whether or not the asynchronous input signal is present or absent within a prescribed detection interval. In addition, the first output signal is asynchronous with the system clock signal. The recovery circuit receives the system clock signal and the first output signal, and outputs a recovery signal. The recovery signal indicates a loss of the asynchronous input signal over a predetermined length of time, and is used to initiate a recovery from the loss of the asynchronous signal. The present arrangement allows a local reset that is both graceful and synchronous with the system clock signal, and does not require shutting down and restarting the communication link. Additionally, the cost of such a reset is only the loss of a few data packets, which can easily be handled by upper-layer error control protocols.
According to another aspect of the invention, a method is provided for
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