Automatic reconfiguration of multiple-way cache system allowing

Details Automatic reconfiguration of multiple-way cache system allowing Automatic reconfiguration of multiple-way cache system allowing

1996-01-05

1997-09-09

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

364DIG1, 3642434, 36424341, 711 3, 711129, 711141, G06F 1208, G06F 1300

Patent

active

056665130

ABSTRACT:
A multi-set cache module is initiated by a maintenance subsystem to function with all sets on-line or only some sets on-line. A parity error sensing switch flip-flop unit will selectively disable only those sets which indicate parity error problems except when multiple simultaneous "hit" signals occur, in which case, the switch unit disables all of the cache sets.

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patent: 5367653 (1994-11-01), Coyle et al.
patent: 5410669 (1995-04-01), Biggs et al.
patent: 5446863 (1995-08-01), Stevens et al.
patent: 5500814 (1996-03-01), Kinoshita et al.
patent: 5522056 (1996-05-01), Watanabe et al.
patent: 5537609 (1996-07-01), Whittaker et al.

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