Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-08-21
2004-08-31
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06785871
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to finding periodic structures in a layer of an integrated circuit that have identical optical properties. More specifically, but without limitation thereto, the present invention relates to finding an optically periodic structure in a cell layer of an integrated circuit design.
BACKGROUND OF THE INVENTION
Photolithography is a common technique employed in the manufacture of semiconductor devices. Typically, a semiconductor wafer is coated with a layer of light-sensitive material, called photoresist. Using a patterned mask, or reticle, the semiconductor wafer is exposed to light, typically actinic radiation, projected through the reticle onto the photoresist, which is chemically altered in the areas exposed to the light. The chemically altered areas of the photoresist are removed by chemical etching, leaving a pattern of photoresist lines on the semiconductor wafer that ideally is identical to the reticle pattern. The photoresist pattern is used to create semiconductor devices on the semiconductor wafer.
The degree to which the resulting photoresist pattern corresponds to the reticle pattern is critical to the fabrication of semiconductor devices on the semiconductor wafer. Errors or deviations from the reticle pattern in the photoresist pattern may result in malfunction of semiconductor devices formed on the semiconductor wafer. The shape and proximity of features in the reticle pattern introduce optical proximity effects such as diffraction that may result in errors and deviations in the photoresist pattern.
The variation of light intensity as a function of position in the image plane of the optical projection system used to project the reticle pattern defines the aerial image. Methods for simulating the aerial image, for example, as described in U.S. Pat. No. 6,171,731, are used in optical proximity correction (OPC) techniques to modify the reticle pattern until the resulting simulated aerial image is within a selected tolerance. The modified reticle pattern is then used to fabricate a mask for the actual production of semiconductor devices on semiconductor wafers.
A standard GDS file format for a cell generally has a hierarchical structure that defines a functional structure in several layers. For example, the GDS file for a memory cell may define cell structures for transistors in a poly layer, interconnections between the transistors in a series of metal layers, and so on. Disadvantageously, the functional structures defined in the GDS file are not suitable for optical proximity correction techniques used in fabricating a production mask, where a description of the hierarchy of the optical geometry of the cell is needed.
SUMMARY OF THE INVENTION
A method of finding an optically periodic structure in a cell layer of an integrated circuit design includes receiving as input a physical representation of a cell layer of an integrated circuit design, finding reference coordinates of a selected portion of the cell layer from the physical representation of a cell layer, selecting an initial element located nearest to the reference coordinates, and constructing a base structure that includes the initial element and a minimum number of elements in the physical representation of the cell layer wherein the base structure may be replicated at an X-offset and a Y-offset to fill the entire selected portion so that for each element in each replica of the base structure there is an identical element at identical coordinates in the physical representation of the cell layer.
REFERENCES:
patent: 5515293 (1996-05-01), Edwards
patent: 5696693 (1997-12-01), Aubel et al.
patent: 5734582 (1998-03-01), Bertolet et al.
patent: 6430737 (2002-08-01), Cobb et al.
patent: 2004/0003366 (2004-01-01), Suzuki
Aleshin Stanislav V.
Egorov Evgueny E.
Rodin Sergei
Fitch Even Tabin & Flannery
LSI Logic Corporation
Thompson A. M.
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