Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-22
2007-05-22
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
10709130
ABSTRACT:
A method, system and program product for generating a process aid on a wafer are disclosed. A “process aid” can be any device provided on a wafer that assists in some process step, but does not ultimately make up part of a usable die. The invention implements libraries of technology design rules, and process aid parameters, and a process aid instruction file library to allow automatic generation of a process aid according to the technology design rules and parameters. As a result, all the inputs required to build a process aid are available up front, which allows the invention to automatically adjust kerf designs to conform to the new technologies. In addition, the invention provides documentation indicating the inputs and details of the process aid produced.
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Bohn Michel E.
Bouchard Pierre J.
Ginter Neil O.
Kunze Derrick J.
Vance Reginald H.
Garbowski Leigh M.
Hoffman Warnick & D'Alessandro LLC
International Business Machines - Corporation
Kotulak Richard M.
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