Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-08-23
2005-08-23
Bragdon, Reginald G. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S170000
Reexamination Certificate
active
06934809
ABSTRACT:
Techniques have been developed whereby likely pointer values are identified at runtime and contents of corresponding storage location can be prefetched into a cache hierarchy to reduce effective memory access latencies. In some realizations, one or more writable stores are defined in a processor architecture to delimit a portion or portions of a memory address space.
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Chaudhry Shailender
Tremblay Marc
Bragdon Reginald G.
Sun Microsystems Inc.
Zagorin O'Brien Graham LLP
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