Automatic prefetch of pointers

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S170000

Reexamination Certificate

active

06934809

ABSTRACT:
Techniques have been developed whereby likely pointer values are identified at runtime and contents of corresponding storage location can be prefetched into a cache hierarchy to reduce effective memory access latencies. In some realizations, one or more writable stores are defined in a processor architecture to delimit a portion or portions of a memory address space.

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patent: 6076151 (2000-06-01), Meier
patent: 6151662 (2000-11-01), Christie et al.
patent: 6247107 (2001-06-01), Christie
Chi, Chi-Hung and Cheung, Chin-Ming, “Hardware-Driven Prefetching for Pointer Data References,” 1998 International Conference on Supercomputing, Melbourne, Australia, 1998, pp. 379-384.
Cooksey, Robert, Colarelli, Dennis and Grunwald, Dirk, “Content-Based Prefetching: Initial Results,” Second International Workshop, IMS 2000, 2000, pp. 33-55.
Liu, Yue, Dimitri, Mona and Kaeli, David R., “Branch-Directed and Pointer-Based Data Cache Prefetching,” Journal of Systems Architecture, vol. 45, No. 12-13, 1999, pp. 1047-1073.

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