Automatic pre-scaler control for a phase-locked loop

Details Automatic pre-scaler control for a phase-locked loop Automatic pre-scaler control for a phase-locked loop

2005-03-29

2005-03-29

Ghebretinsae, Temesghen (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000, C375S376000, C327S148000, C327S157000

Reexamination Certificate

active

06873670

ABSTRACT:
A phase locked loop (PLL) system is arranged to automatically adjust the pre-scaler divide ratio. The PLL includes a phase-frequency detector circuit that compares a feedback clock signal to an input clock signal to provide UP and DOWN signals. A charge-pump circuit provides an oscillator control signal in response to UP and DOWN. A VCO produces an oscillator signal in response to the oscillator control signal. A first divider circuit provides an output clock signal in response to the oscillator signal, where an up-down counter circuit controls the divider ratio. A second divider circuit provides the feedback clock signal in response to the output clock signal. The up-down counter evaluates the output of the window comparator, which analyzes the oscillator control signal for proper operation with the VCO.

REFERENCES:
patent: 4392253 (1983-07-01), Yamada et al.
patent: 5202906 (1993-04-01), Saito et al.
patent: 6496556 (2002-12-01), Huehne et al.
patent: 6747519 (2004-06-01), Jaehne et al.
patent: 20030165209 (2003-09-01), Chen et al.
Edited by Behzad Razavi, Monolithic Phase-locked Loops and Clock Recovery Circuits, Theory and Design,IEEE Press, 1996, Section 4.8, pp. 15-16.

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