Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-08-28
2003-01-07
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06505333
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of automatic placement and routing of a semiconductor integrated circuit in semiconductor circuit design.
2. Description of the Prior Art
FIG. 6A
is a wiring diagram showing a result of a global routing step according to a conventional method of automatic placement and routing of a semiconductor integrated circuit, and
FIG. 6B
illustrates a shape of a via or via shape. In the drawings, the reference numeral
601
-
606
are resultant wirings of the global routing step;
601
,
602
, and
604
designate a first wiring on a layer A;
603
,
605
, and
606
designate a second wiring on a layer B; and
607
designates a via connecting the first wiring
604
to the second wiring
603
. In addition, the reference numeral
608
designates a via shape with a cross-form pattern;
609
designates a vertical routing track; and
610
designates a horizontal routing track. The via shape
608
is prepared previously as a library with other functional blocks such as gate and flip-flop prior to the global routing step. Note that in
FIG. 6A
, a search unit is provided with a small area of 5 tracks×5 tracks.
A layout for the above semiconductor integrated circuit is to produce an artwork data as to wirings of the whole chip when a logic circuit diagram described with the functional block prepared in the library and a formation of a semiconductor chip are provided. Nowadays, there is proposed an automatic layout system which enables the production of the artwork data without errors for a short time period and which is put into practice.
In order to simplify general layout problems in accordance with a larger scale of circuits to be targeted, the automatic layout system (not depicted) deals with an automatic placement and routing flow which are divided into three steps of a placement step, a global routing step, and a detailed routing step, and processed in this turn.
The operation will be next described, referring to a flow chart in a global routing step of FIG.
8
.
Prior to an implementation of the global routing step, a technology file is first produced, and a library including layout patterns is produced in a placement step. From the library, a reading of logic connection information such as gate circuit and flip-flop is carried out, and a placement of functional blocks is carried out on a semiconductor chip based on that information, a placement result including design information upon completion of the placement is filed previously in a database and the like
Then, based on the filed placement result (ST
501
), a global wiring route is determined (ST
502
), and the number of wirings to be used is made an estimate in each search unit (ST
503
). Herein, the via shape is not considered yet. In addition, the step ST
502
and the step ST
503
serve as a global routing function together, and are carried out simultaneously or in turn. Finally, the resultant wirings are verified whether to be possible (ST
504
).
Here, when it is determined as “wiring possible”, a set of flow of the global routing step is brought to an end, while when it is determined as “wiring impossible”, the steps ST
502
an ST
503
are carried out again. In the second or later steps ST
502
and ST
503
, an improvement is carried out based on the repetitive results at the global routing step. Incidentally, in the steps ST
504
, the global routing step may be brought to an end by other conditions such as practice time.
However, in the prior art, since the via shape and/or the number of via holes were not considered at the global routing step, in a result of the subsequent detailed routing step, as shown in
FIG. 7
, the first wiring
602
and the second wiring
605
to be passed on wire grids determined as “unusable” (see wire grids
107
,
108
and the like described later) failed to be wired due to the placement of the via
607
.
Since the conventional method of automatic placement and routing of a semiconductor integrated circuit is configured as described above, in the automatic placement and routing, the via shape was not considered at the global routing step making an estimate of wirings. For this reason, at the detailed routing step of carrying out actually a layout, when a via is, allocated with a large-sized one, a “wiring impossible” state such that its neighboring routing tracks become unusable may be occurred, or a layout quite different from the estimated wiring route determined at the global routing step may be completed.
In the case of such a “wiring impossible” state, a LSI cannot operate, and in the case of the wrong wiring route, the control of timings and the like may be difficult.
SUMMARY OF THE INVENTION
The present invention is made to solve such a problem, and it is an object to provide a method of automatic placement and routing of a semiconductor integrated circuit capable of making an estimate of wiring routes with good precision while a high-speed process on wiring estimates is maintained.
According to a first aspect of the present invention, there is provided a method of automatic placement and routing of a semiconductor integrated circuit with a global routing step, said step comprising: a first step of, based on a placement result in which a functional block included in a library is placed on a semiconductor chip, determining a global wiring route by considering a shape of a via in a connecting point between layers and then considering a wire grid to be unusable by an allocation of the via; a second step of counting the number of routing tracks to be used in each certain search unit; and a third step of determining a wiring actually whether to be possible by verifying a determined result of the global wiring route at the first step and a counted result of the routing tracks to be used at the second step.
According to a second aspect of the present invention, there is provided a method of automatic placement and routing of a semiconductor integrated circuit with a global routing step, said step comprising: a first step of, based on a placement result in which a functional block included in a library is placed on a semiconductor chip, determining a global wiring route by considering the number of a plurality of via allocations in a connecting point between layers and then considering a wire grid to be unusable by the via allocations; a second step of counting the number of routing tracks to be used in each certain search unit; and a third step of determining a wiring actually whether to be possible by verifying a determined result of the global wiring route at the first step and a counted result of the routing tracks to be used at the second step.
According to a third aspect of the present invention, there is provided a method of automatic placement and routing of a semiconductor integrated circuit with a global routing step, said step comprising: a first step of, based on a placement result in which a functional block included in a library is placed on a semiconductor chip, determining a global wiring route by considering a shape of a via in a connecting point between layers and then considering a wire grid to be unusable by an allocation of the via; a second step of counting the number of routing tracks to be used in each certain search unit by considering the shape of the via and then considering a wire grid to be unusable by an allocation of the via; and a third step of determining a wiring actually whether to be possible by verifying a determined result of the global wiring route at the first step and a counted result of the routing tracks to be used at the second step.
According to a fourth aspect of the present invention, there is provided a method of automatic placement and routing of a semiconductor integrated circuit with a global routing step, said step comprising: a first step of, based on a placement result in which a functional block included in a library is placed on a semiconductor chip, determining a global wiring route by considering the number of a plurality of via allocations in
Burns Doane , Swecker, Mathis LLP
Lin Sun James
Mitsubishi Denki & Kabushiki Kaisha
Siek Vuthe
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