Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-12-03
2001-06-26
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06253364
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic placement and routing device for use in the layout design of a semiconductor integrated circuit and for automatically constructing also a bus structure in placing cells which constitute the semiconductor integrated circuit in position and routing wires for interconnection between the cells.
2. Description of the Background Art
FIG. 26
is a block diagram of a conventional automatic placement and routing device. As shown in
FIG. 26
, logic circuit information
2
and constraint information
3
are provided to logic circuit information analysis means
5
and constraint information analysis means
6
, respectively.
The logic circuit information
2
is text or data information which specifies a logic circuit including a bus structure in netlist format. The constraint information
3
is text or data information which specifies constraints such as (1) timing, (2) power consumption, (3) voltage drop, (4) skew and (5) signal noise resistance which are imposed upon the logic circuit specified by the logic circuit information
2
.
The logic circuit information analysis means
5
and the constraint information analysis means
6
analyze the logic circuit information
2
and the constraint information
3
to output analysis results to a logic circuit information holding portion
8
and a constraint information holding portion
9
, respectively. The logic circuit information holding portion
8
and the constraint information holding portion
9
hold the respective analysis results therein.
Cell placement means
10
places cells in position based on the information held in the logic circuit information holding portion
8
and the information held in the constraint information holding portion
9
. Placement information extraction/verification means
11
extracts (holds) and verifies information about the cell placement (referred to hereinafter as cell placement information).
Global routing means
19
performs global routing for constructing wire paths for interconnection between the cells, based on the cell placement information extracted by the placement information extraction/verification means
11
. Global routing information extraction/verification means
20
extracts (holds) and verifies the global routing result.
Detail routing means
21
performs detail routing in consideration for the layout of wires for interconnecting inputs and outputs of the cells, based on the global routing result extracted by the global routing information extraction/verification means
20
. Detail routing information extraction/verification means
22
extracts and verifies the detail routing result, and thereafter a routing result holding portion
23
holds the detail routing result therein.
Routing result output means
24
outputs the detail routing result held by the routing result holding portion
23
in the form of a visually recognizable routing result
25
.
The conventional placement and routing device has thus performed the placement and routing based on the logic circuit information
2
pertaining to the logic circuit including the bus structure which is specified prior to the placement and routing.
It has hence been difficult to provide a placement and routing result with a satisfactory bus structure on an LSI circuit. Additionally, a change in the bus structure requires a manual modification to the logic circuit information (netlist) itself. The time required for the modification has resulted in an increased time period required for designing the logic circuit.
Further, the conventional automatic placement and routing device does not take the bus structure into consideration for the placement and routing, to render the wires serving as buses longer than necessary, causing the deterioration of characteristics such as the decrease in operating speed and degree of integration, and the increase in power consumption. This results from the fact that the bus structure included in the logic circuit information is constructed without reflecting the placement and routing of the cells.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, an automatic placement and routing device comprises: cell placement information output means receiving logic circuit information specifying a logic circuit in netlist format for outputting cell placement information specifying the placement of cells constituting the logic circuit, based on the logic circuit information; bus structure construction result output means receiving the logic circuit information, the cell placement information, and bus information specifying transfer of signals between the cells on a logical level for constructing a bus structure including signal lines for making connection between the cells, based on the logic circuit information, the cell placement information and the bus information, to output a bus construction result; and routing establishment means receiving the bus construction result for establishing routing between the cells, based on the bus construction result.
Preferably, according to a second aspect of the present invention, the automatic placement and routing device of the first aspect further comprises global routing result output means for performing global routing for constructing wire paths for interconnection between the cells, based on the cell placement information, to output a global routing result, wherein the bus structure construction result output means outputs the bus construction result, based on the global routing result in addition to the logic circuit information, the cell placement information and the bus information.
Preferably, according to a third aspect of the present invention, the automatic placement and routing device of the first aspect further comprises: global routing result output means for performing global routing for constructing wire paths for interconnection between the cells, based on the cell placement information, to output a global routing result; and detail routing result output means for performing detail routing which is routing in consideration of a layout for connection between the cells, based on the global routing result, to output a detail routing result, wherein the bus structure construction result output means outputs the bus construction result, based on the detail routing result in addition to the logic circuit information, the cell placement information and the bus information.
Preferably, according to a fourth aspect of the present invention, in the automatic placement and routing device of the first aspect, the bus structure construction result output means comprises bus structure construction means for providing the signal lines to construct the bus structure, the bus structure construction means comprising: cluster construction means for combining a plurality of cells and existing clusters which satisfy a predetermined condition together to construct a new cluster; in-cluster connection construction means for constructing signal lines for making connection between cells in the cluster constructed by the cluster construction means; and operation control means for causing the cluster construction means and the in-cluster connection construction means to continue their operations until the cluster covers all of the cells constituting the logic circuit.
Preferably, according to a fifth aspect of the present invention, in the automatic placement and routing device of the fourth aspect, the bus information includes information which specifies control of the transfer of signals between cells on a logical level, and the bus structure includes a bus control signal for controlling the continuity/cutoff of each of the signal lines; and the bus structure construction result output means further comprises bus control signal construction means for constructing the bus control signal independently of the bus structure construction means.
Preferably, according to a sixth aspect of the present invention, in the automatic placement and routing device of the fifth aspect, th
Shimazu Yukihiko
Tanaka Genichi
Burns Doane , Swecker, Mathis LLP
Kik Phallaka
Mitsubishi Denki & Kabushiki Kaisha
Smith Matthew
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