Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-07-12
2004-07-13
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06763510
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic placement and routing apparatus, automatic placement and routing method, and automatic placement and routing program that are of use for designing a semiconductor integrated circuit.
2. Description of the Prior Art
FIG. 10
is a block diagram illustrating a conventional automatic placement and routing apparatus. In
FIG. 10
, there are shown a net list
101
, constraint information
102
, a library
103
, a read means
104
, a placement means
105
, a logic optimization means
106
, and a routing means
107
. In the net list
101
, specified are information concerning cells constituting a logic circuit, information concerning nets defining connectional relations between the cells of the logic circuit, and information concerning logic layers that divide the logic circuit into an appropriate size. The constraint information
102
defines various constraints on logic circuits, such as routing delay, power consumption, and signal integrity. The library
103
registers the cells used for designing the layout of a logic circuit. The read means
104
reads the net list
101
and the constraint information
102
. The placement means
105
places the cells registered in the library
103
on the basis of the net list
101
. The logic optimization means
106
analyzes, each time a cell forming a specific region of a logic circuit is arranged by the placement means
105
, the layout of the logic circuit in that region, performs a logic optimization that rewrites the net list
101
of the logic circuit in that region so as to satisfy the constraints defined in the constraint information
102
, and modifies the layout of the logic circuit in that region on the basis of the rewritten net list. The routing means
107
routes, after the logic optimization means
106
performs a logic optimization and a layout modification over the entire logic circuits, the cells so as to satisfy the connectional relations defined in a net list
108
of all the rewritten logic circuits. The logic optimization means
106
outputs the net list
108
of all the rewritten logic circuits.
Next, the operation will be described.
FIG. 11
is a flow chart for a conventional automatic placement and routing method.
First, the read means
104
reads the net list
101
and the constraint information
102
(step ST
101
).
Thereafter, the placement means
105
fetches the net list
101
from the read means
104
. Then, on the basis of the net list
101
, the placement means
105
places the cells registered in the library
103
. Also, the logic optimization means
106
fetches the net list
101
and the constraint information
102
from the read means
104
. In addition, each time a cell forming a specific region of a logic circuit is arranged by the placement means
105
, the logic optimization means
106
analyzes the layout of the logic circuit in that region, performs a logic optimization that rewrites the net list
101
of the logic circuit in that region so as to satisfy the constraints defined in the constraint information
102
, and modifies the layout of the logic circuit in that region on the basis of the rewritten net list (step ST
102
). The net list
101
is rewritten when anew cell and net, for example, are added.
After the logic optimization means
106
performs the logic optimization and the layout modification over the entire logic circuits, the routing means
107
routes the cells so as to satisfy the connectional relations defined in the net list
108
of all the rewritten logic circuits (step ST
103
).
Thereafter, the logic optimization means
106
outputs the net list
108
of all the rewritten logic circuits (step ST
104
).
The steps ST
103
and ST
104
may be replaced in the order.
FIG. 12
illustrates an example of the contents defined in the net list of a logic circuit before a logic optimization in the conventional example. In
FIG. 12
, there are shown a first to a fourth buffer circuit cell
111
to
114
constituting the logic circuit, a logic layer
115
furnished with the first buffer circuit cell
111
and the second buffer circuit cell
112
, a net
116
that crosses the logic layer
115
, and a port
117
that is located on the boundary of the logic layer
115
where the net
116
passes through. The net
116
represents that the second through fourth buffer circuit cells
112
to
114
are connected to one another in parallel, and the first buffer cell
111
is connected in series to the second through fourth circuit buffer cells
112
to
114
.
FIG. 13
illustrates an example of the contents defined in the net list of a logic circuit after a logic optimization in the conventional example. In
FIG. 13
, there are shown a newly added buffer circuit cell
118
that is added to the net
116
in order to improve the routing delay from the first buffer circuit cell
111
to the second buffer circuit cell
112
and the third buffer circuit cell
113
, a newly net
119
produced by the buffer circuit cell
118
being added to the net
116
, and a newly port
120
produced by the buffer circuit cell
118
being added to the net
116
, located on the boundary of the logic layer
115
where the net
119
passes through. The other components are identical or equal to those illustrated with the same symbols in
FIG. 12
, and the detailed explanations will be omitted. The net
116
represents that the first buffer circuit cell
111
and the fourth buffer circuit cell
114
and the added buffer circuit cell
118
are in the connectional relation; and the net
119
represents that the added buffer circuit cell
118
and the second buffer circuit cell
112
and the third buffer circuit cell
113
are in the connectional relation.
Thus, in some cases, the conventional automatic placement and routing apparatus and automatic placement and routing method may increase the number of the ports located on the boundary of the logic layer
115
through the process of a logic optimization. Therefore, there can be a case that the same test pattern cannot be used before and after a logic optimization, which presents a problem of effective use of the test patterns.
SUMMARY OF THE INVENTION
The present invention has been made in view of the foregoing, and an object of the invention is to provide an automatic placement and routing apparatus and automatic placement and routing method that performs a logic optimization so as not to alter the number of ports located on the boundary of a logic layer, and an automatic placement and routing program that makes a computer perform such a logic optimization function.
According to a first aspect of the present invention, there is provided an automatic placement and routing apparatus including: a placement means that places cells registered in a library, on the basis of logic circuit information in which are specified information concerning the cells constituting a logic circuit, information concerning nets defining connectional relations between the cells constituting the logic circuit, and information concerning logic layers that segment the logic circuit into appropriate sizes; a routing means that routes the cells so as to satisfy connectional relations defined in the logic circuit information; a distinguishing information adding means that analyzes the logic circuit information, and adds distinguishing information that differentiates one portion with a port located on a boundary of a logic layer on a net crossing the logic layer as the boundary from another portion to each of the portions; and a logic optimization means that executes a logic optimization to rewrite the logic circuit information, in such a manner that the number of ports located on the boundary of the logic layer is not altered by using the distinguishing information.
Therefore, the same test patterns before and after the logic optimization is available, resulting in an effective use of the test patterns.
According to a second aspect of the present invention, there is an automatic placement and routing method incl
Garbowski Leigh M.
Renesas Technology Corp.
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