Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2007-06-11
2011-11-01
Portka, Gary (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C707S813000
Reexamination Certificate
active
08051266
ABSTRACT:
The present invention manages the execution of multiple AMM cycles to reduce or eliminate any overlap. Specifically, the present invention provides an external supervisory process to monitor the AMM behavior of VMs on one or more nodes, and intervene when coincident AMM activity appears to be imminent. If AMM patterns suggest that two VMs are likely to perform a (e.g., a major) AMM cycle simultaneously (or with significant overlap) in the near future, the supervisory process can trigger one of the VMs to AMM immediately, or at the first ‘safe’ interval prior to the predicted AMM collision. This will have the effect of desynchronizing the AMM behavior of the VMs and maintaining AMM latency for both VMs within the expected bounds for their independent operation, without any inter-VM effects.
REFERENCES:
patent: 2007/0033240 (2007-02-01), Barsness et al.
patent: 2008/0281886 (2008-11-01), Petrank et al.
DeVal Gary J.
Hrischuk Curtis E.
Carey, Rodriguez, Greenberg & Paul
Greenberg, Esq. Steven M.
International Business Machines - Corporation
Portka Gary
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