Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-03-25
2001-11-06
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C438S014000
Reexamination Certificate
active
06314548
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic maximum theoretical yield calculating apparatus for obtaining chip layout for producing the maximum number of chips from a wafer at the time of producing chips from a wafer, automatically calculating the maximum theoretical yield of chips and also automatically calculating specifications of an exposing device to realize production of chips with the minimum number of times of exposure and a computer-readable recording medium storing programs to execute automatic calculation of maximum theoretical yield with a computer.
2. Description of the Related Art
It is very effective, in manufacture of semiconductor devices, for cost reduction of products to design the layout of chips on the wafer to obtain the maximum number of chips in view of obtaining the theoretical maximum number of chips from a sheet of wafer and obtain the so-called maximum theoretical yield through the manufacture under the design explained above. It is because the manufacturing unit price per chip or product can be lowered by increasing the number of chips per water, namely raising the yield, since wafer cost is generally not different to a large extent in the same manufacturing method in the single line.
For example, when chip layout in the area effective to manufacture i.e. the effective range of a wafer aiming at the theoretical yield of fifty-eight as shown in
FIG. 27A
is compared with the chip layout aiming at the theoretical yield of sixty-one as shown in
FIG. 27B
, the latter layout is apparently advantageous from the viewpoint of manufacturing cost.
A method of obtaining such maximum theoretical yield is disclosed, for example, in the Japanese Published Unexamined Patent Application No. Sho 63-250811 entitled as “Semiconductor Wafer”.
However, in this Japanese Published Unexamined Patent Application No. Sho 63-250811, a calculation example for determining the chip layout on a wafer to obtain the maximum number of chips, namely the maximum theoretical number of chips is disclosed but it is difficult to apply this calculation result to the actual wafer manufacturing process.
It is because chip layout is determined by a semiconductor exposing device such as a stepper, and so forth in the actual wafer manufacturing process and therefore layout for assuring the maximum theoretical yield cannot be realized unless various specifications for determining the exposing layout by the semiconductor exposing device are automatically provided in the chip layout for obtaining the maximum theoretical yield.
In other words, in the wafer manufacturing process, a plurality of chips are generally grouped by a sheet of mask and these chips are exposed on the wafer under this condition with a wiring pattern printing device which is called a semiconductor exposing device. In this timing, since the semiconductor manufacturing line is required to raise productivity per a short period of time, it is a very important factor for improvement of the productivity, in the layout for obtaining the same theoretical yield, how to reduce the number of times of exposing process for the layout of chips.
For example, when the theoretical yield is sixty-one as shown in FIG.
28
A and
FIG. 28B
, the layout shown in
FIG. 28B
in which the number of times of exposing process is nineteen is apparently more advantageous in the point of view of manufacturing cost than the layout shown in
FIG. 28A
in which the number of times of exposing process is twenty-one.
However, the method to realize the minimum number of times of exposing process assuring the maximum theoretical yield is not yet proposed.
SUMMARY OF THE INVENTION
With the background explained previously, the present invention has been proposed to provide an automatic maximum theoretical yield calculating apparatus to realize the minimum number of times of exposing process with the maximum theoretical yield and a computer-readable recording medium storing a program to execute automatic calculation for the maximum theoretical yield with a computer.
The automatic maximum theoretical yield calculating apparatus of the present invention is provided with the means for solving the subject of the related art explained above comprising:
initial data means including a wafer shape specification storing function, wafer effective area specification input/storing function, chip size specification input/storing function and exposing size specification input/storing function;
virtual chip layout calculating means;
virtual chip layout storing means;
maximum theoretical yield layout determining means including the maximum theoretical yield condition retrieving function and maximum theoretical yield condition selecting means;
virtual exposure layout calculating means including an exposure layout calculating function and an exposing number calculating function;
virtual exposure layout storing means;
minimum exposure layout determining means including a minimum exposure number condition retrieving function and a minimum exposure number condition selecting function; and
determined layout displaying means including determined layout displaying function and an exposing device specification displaying function.
In this automatic maximum theoretical yield calculating apparatus, a specification for determining the shape of a wafer in a plurality of sizes is stored first by the wafer shape specification storing function in the initial data means, an input specification is then stored when the specification is an input to determine the shape of an effective area to determine the chip manufacturing range on the wafer by the wafer effective area specification input/storing function, an input specification is then stored when the specification is input to determine the size of the chips to be arranged by the chip size specification input/storing function and input specification is stored when the specification is input to determine the range of a single exposing process and the number of chips within this range by the exposure size specification input/storing function.
Next, in the virtual chip layout calculating means, calculation is conducted, by the chip layout calculating function, for determining virtual chip layout in the effective area, under the condition of chip layout depending on a plurality of relative positions of the wafer center and the chip including this wafer center, based on the wafer shape and shape of the effective area obtained from the specification for determining the shape of wafer and the specification for determining the shape of effective area stored in the initial data means and the number of chips providing the theoretical yield in the effective area of the chip layout is calculated by the chip layout calculating function.
Next, in the virtual chip layout storing means, chip layout condition depending on a plurality of relative positions of the wafer center and the chip including such wafer center and theoretical yield obtained by the theoretical yield calculating function based on such condition are stored.
Next, in the maximum theoretical yield layout determining means, a layout condition assuring the maximum theoretical yield is retrieved from the theoretical yield stored in the virtual chip layout storing means obtained by the virtual chip layout calculating means and is then stored by the maximum theoretical yield condition retrieving function and the desired condition is selected from a plurality of layout conditions, when these are existing, which provide the maximum theoretical yield retrieved and stored by the maximum theoretical yield condition selecting means.
Next, in the virtual exposure layout calculating means, the exposure layout condition for the virtual exposure of the wafer by the semiconductor exposing device is calculated under the layout condition which provides the maximum theoretical yield selected by the maximum theoretical yield condition selecting function in the maximum theoretical yield layout determining means by the exposure layout calculating function and th
Kananen Ronald P.
Rader Fishman & Grauer
Siek Vuthe
Smith Matthew
Sony Corporation
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