Automatic logic designing method and system

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364488, G06F 1750

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active

055046908

ABSTRACT:
An automatic logic designing method and system in which a control table describing a condition and a behavior corresponding to the condition which express the specification of a computer is inputted and processed in a processor so that a logic circuit having no redundancy which can be easily seen by the designer is designed at a high speed. The control table is converted into the logic circuit whose function is expressed by a detailed Boolean expression. In an instance, selector logics are allocated in consideration of the polarity of the logic. A redundancy detection process or a redundancy logic elimination process is executed for the redundancy logics designated by a redundancy indicate file. A signal name which can be easily understood by the logic designer is formed. An implementing system includes an input control table file, a functional structure converting section of a conditional equation and a behavioral structure, a regular logic expanding processing section, and a redundancy logic elimination processing section, so that the logic circuit formed is outputted to a Boolean expression file.

REFERENCES:
patent: 4703435 (1987-10-01), Darringer et al.
patent: 5005136 (1991-04-01), Van Berkel et al.
patent: 5029102 (1991-07-01), Drumm et al.
patent: 5258919 (1993-11-01), Yamanouchi et al.
patent: 5274793 (1993-12-01), Kuroda et al.
patent: 5287289 (1994-02-01), Kageyama et al.
patent: 5299137 (1994-03-01), Kingsley
patent: 5331569 (1994-07-01), Iijima
patent: 5359537 (1994-10-01), Saucier et al.
"Table Driven System," Information Processing Society of Japan, The 29th National Conference, 1984, pp. 91-92. (Japanese).
Gregory, David, et al. "Socrates: A System for Automatically Synthesizing and Optimizing Combinational Logic," The Design Automation Conference, 1986, pp. 79-85. (English).
Rudell, Richard L., et al. "Multiple-Valued Minimization for PLA Optimization," IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 5, Sep. 1987, pp. 727-750. (English).

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