Automatic latch compression/reduction

Details Automatic latch compression/reduction Automatic latch compression/reduction

2006-06-06

2006-06-06

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07058914

ABSTRACT:
The disclosure presents a method of designing an integrated circuit having latches. The invention first prepares a logical design of logic devices and latches and then creates a physical design by positioning the logic devices and the latches within the integrated circuit based on the logical design. During the process of creating the physical design the invention eliminates redundant latches by combining latches which do not transition during the same clock cycle, latches which do not relate to the same logical function, latches which are in the same clock domain, and latches that are within a given physical proximity of each other.

REFERENCES:
patent: 5515526 (1996-05-01), Okuno
patent: 5822217 (1998-10-01), Shenoy
patent: 6023568 (2000-02-01), Segal
patent: 2003/0126579 (2003-07-01), Whitaker et al.
patent: 2003/0182638 (2003-09-01), Gupta et al.
patent: 2004/0261043 (2004-12-01), Baumgartner et al.
patent: 2002093188 (2003-03-01), None

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