Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-08
2003-12-23
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06668360
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the qualifying of circuits and process parameters used to create integrated circuit cell libraries. More particularly, this invention relates to the automatic qualification of many varied circuits and circuit cell libraries which are created by multiple independent design groups and which are used on the same chip die.
2. Description of Related Art
Today, many integrated circuit (IC) designers face the problem of both errors in the circuits themselves and incompatibility caused by different modeling properties from various system macros coming from different design groups. It is the job of the circuit provider to make sure that the delivered design is error free and models and simulates correctly. This verification flow is shown in FIG.
1
. All of the steps, which follow below, have tools or application programs available, which allow the computer to assist in the design. Also, the actual design databases, including design rules which govern spacing of wiring on the chip design, simulation models of the logic blocks, technology definition including the semiconductor layout of the transistors and the integrated circuit database which describes the function of the transistors, all reside on the computer. These design databases interface with the software tools. The accuracy of the databases and the design tools will increase the success of designers achieving their objective of error-free designs which work the first time they are fabricated in silicon. This fact causes designers of integrated circuits to invest heavily in design tools and design database technology.
FIG. 1
shows the High Level Design
110
, which is a formal description of the functional idea, which is to be implemented in circuitry. The high-level design
110
can consist of a written document with high level flow diagrams and/or a high level description in a hardware description language such as HDL. The detailed schematic
120
contains functional inputs and outputs of the integrated circuit, which interface with other circuits on a silicon chip or with the primary inputs and outputs of the silicon chip. It also includes a definition of major macros or sub-functional islands such as an Industry Standard Data Network (ISDN) macro, PC bus interface logic which follows the input/output adapter specification for today's personal computers, a memory subsystem and read only memory (ROM). In
FIG. 1
, logic design synthesis
130
, is where logical AND & OR blocks are designed or automatically generated from hardware description language (HDL) descriptions of the design from the high level design
110
and the detailed schematic
120
. The AND & OR blocks which result from synthesis are then simulated
140
and tested by applying user-supplied test patterns which test the circuit output function based on the circuit input signals. Simulation
140
allows designers and users of integrated circuits to verify the lower level implementation of the high level design. For instance, the HDL, high level design, is simulated with a set of HDL stimulation test patterns. These same HDL simulation test patterns can be run against the lower level AND/OR synthesized designs. If the low-level logical outputs are checked against the logical outputs of the high-level design descriptions, the synthesis operation was a success.
Next, it is necessary to do physical placement and routing
150
of transistors, electronic components, and wiring using a given semiconductor ground rule set for making integrated circuits on a semiconductor substrate. It represents the physical placement or layout of logic macros or building blocks, such as counters, ANDs, ORs, inverters, and other higher level blocks such as Industry Standard Data Network (ISDN) communication controllers. The placement algorithms use knowledge of the input of the blocks and output lists to optimize the placement of the macros on a silicon die area. Next, a wiring program does the actual connecting of the macro input/output wires between the previously placed macros.
Next, the merging
160
of the physical integrated circuit dimensions of the macros and of the wires connecting the macros. The physical merge is accompanied by a design rule check (DRC) to be sure that the inter-wire spacing rules, device size rules, resistive and capacitive rules are obeyed after the physical merge process has been completed. Then, the final, exhaustive layout verification
170
is done. This step guarantees that the circuit in the mask layout matches the schematic description. This step isolates all connectivity problems. It allows for the merging or importation of other previously designed and verified integrated circuits, which were designed by other groups at other times.
U.S. Pat. No. 5,956,256 (Rezek, et al.) describes a method and apparatus for optimizing a circuit design having multiple cycle-paths. The circuit design having a number of multiple cycle paths may be optimized by identifying at least one of the number of multiple-cycle paths within the circuit design, and identifying the corresponding associated the multiple-cycle paths and replacing those clocks with qualified clocks. The circuit design using qualified replacement clocks is optimized with a standard optimization tool.
U.S. Pat. No. 4,922,432 (Kobayashi, et al.) provides a computer-aided design system and method for designing an application specific integrated circuit which enables a user to define functional architecture independent specifications for the integrated circuit and which translates the functional architecture independent specifications into the detailed information needed for directly producing the integrated circuit. The functional architecture independent specifications of the desired integrated circuit can be defined at the functional architecture independent level in a flowchart format.
U.S. Pat. No. 5,348,902 (Shimada, et al.) describes a method of designing cells applicable to different design automation systems. The cell circuits designed by the different design automation systems, respectively, are demarcated into a logic function portion and an input/output portion. Sets of common lithography patterns for the logic function portions of the cells are determined such that each common lithography pattern set is shared by those cells which have same logic function in the different automation systems.
U.S. Pat. 5,831,868 (Beausang, et al.) describes a computer implemented process and system for providing a test ready compiler with specific information regarding the impact of added scannable cells and resources on its design. In so doing, the test ready compiler optimizes more effectively for added test resources (e.g., scannable cells and other scan routing resources) so that predetermined performance and design related constraints of the design are maintained.
U.S. Pat. No. 6,058,252 (Noll, et al.) describes a system and method for generating effective layout constraints for a circuit design. A netlist data structure representing a circuit configuration has multiple circuit elements and represents static timing information for the circuit configuration. Specified circuit elements to be used for generating the layout constraints are selected. A most critical path through each of the specified circuit elements is identified based upon the static timing information. The layout constraints are generated from the most critical path through each of the specified circuit elements.
SUMMARY OF THE INVENTION
It is the objective of this invention to provide a method for automatically verifying one or several integrated circuits created by one or several design groups. The steps involved in this automatic verification of circuits begin with creating a technology definition database, which details the semiconductor parameters for the for the electronic devices used in the circuits being verified. Next, the simulation model database is created. This database allows the simulation and verification of the logic design of the designer
Ackerman Stephen B.
Bowers Brandon
Garbowski Leigh M.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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