Automatic generation of streaming data interface circuit

Details Automatic generation of streaming data interface circuit Automatic generation of streaming data interface circuit

2005-09-20

2009-10-13

Tsai, Henry W. H. (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S008000, C710S062000, C710S072000, C712S002000, C712S007000, C712S009000

Reexamination Certificate

active

07603492

ABSTRACT:
A streaming data interface device (700) of a streaming processing system (200) is automatically generated by selecting a set of circuit parameters (610) consistent with a set of circuit constraints and generating (612, 614) a representation of a candidate memory interface device based upon a set of stream descriptors. The candidate streaming data interface device is evaluated (616) with respect to one or more quality metrics and the representation of the candidate streaming processor circuit is output (622) if the candidate memory interface device satisfies a set of processing system constraints and is better in at least one of the one or more quality metrics than other candidate memory interface devices.

REFERENCES:
patent: 5535319 (1996-07-01), Pascoe et al.
patent: 5694568 (1997-12-01), Harrison et al.
patent: 5699277 (1997-12-01), Munson et al.
patent: 5854929 (1998-12-01), Van Praet et al.
patent: 5856975 (1999-01-01), Rostoker et al.
patent: 6023579 (2000-02-01), Hellgren et al.
patent: 6172990 (2001-01-01), Deb et al.
patent: 6195024 (2001-02-01), Fallon
patent: 6195368 (2001-02-01), Gratacap
patent: 6295586 (2001-09-01), Novak et al.
patent: 6408428 (2002-06-01), Schlansker et al.
patent: 6549991 (2003-04-01), Huang et al.
patent: 6591349 (2003-07-01), Steinman et al.
patent: 6647456 (2003-11-01), Van Dyke et al.
patent: 6701515 (2004-03-01), Wilson et al.
patent: 6721884 (2004-04-01), De Oliveira Kastrup Pereira et al.
patent: 6744274 (2004-06-01), Arnold et al.
patent: 6778188 (2004-08-01), Emberling et al.
patent: 6813701 (2004-11-01), Ansari
patent: 6825848 (2004-11-01), Fu et al.
patent: 6892286 (2005-05-01), Hangal et al.
patent: 6925507 (2005-08-01), Hersent
patent: 6941548 (2005-09-01), Goodwin et al.
patent: 6958040 (2005-10-01), Oliver et al.
patent: 7054989 (2006-05-01), Mizobata
patent: 7075541 (2006-07-01), Diard
patent: 7159099 (2007-01-01), Lucas et al.
patent: 7246203 (2007-07-01), Moat et al.
patent: 7305649 (2007-12-01), Bellas et al.
patent: 7392498 (2008-06-01), Srinivasan et al.
patent: 7426709 (2008-09-01), Ganesan
patent: 2002/0046251 (2002-04-01), Siegel
patent: 2002/0133784 (2002-09-01), Gupta et al.
patent: 2002/0151992 (2002-10-01), Hoffberg et al.
patent: 2004/0003206 (2004-01-01), May et al.
patent: 2004/0003220 (2004-01-01), May et al.
patent: 2004/0003376 (2004-01-01), May et al.
patent: 2004/0117595 (2004-06-01), Norris et al.
patent: 2004/0128473 (2004-07-01), May et al.
patent: 2004/0153813 (2004-08-01), Swoboda
patent: 2005/0050252 (2005-03-01), Kuno
patent: 2005/0071835 (2005-03-01), Essick et al.
patent: 2005/0122335 (2005-06-01), MacInnis et al.
patent: 2005/0257151 (2005-11-01), Wu
patent: 2005/0289621 (2005-12-01), Mungula
patent: 2006/0031791 (2006-02-01), Moona et al.
patent: 2006/0044389 (2006-03-01), Chai et al.
patent: 2006/0067592 (2006-03-01), Walmsley et al.
patent: 2006/0242617 (2006-10-01), Bellas et al.
patent: 2006/0265485 (2006-11-01), Chai et al.
patent: 2008/0120497 (2008-05-01), Chai et al.
patent: WO 2004-055667 (2004-07-01), None
“The Reconfigurable Streaming Vector Processor (RSVP)” by Ciricescu et al., Proceedings of the 36th International Symposium on Microarchitecture, 2003.
“Interface Design Approach For System On Chip Based On Configuration” by Maalej et al., Proceedings of the 2003 International Symposium on Circuits and Systems, May 2003.
“Interface Architecture Generation for IP Integration in SoC Design” by Abbes et al., The 2006 International Conference on Computer Engineering and Systems, Nov. 2006.
“Automatic Generation of Interfaces for C-VHDL Cosimulation of Embedded Systems: An Industrial Experience” by Valderrama et al., Proceedings of the Seventh IEEE International Workshop on Rapid System Prototyping, Jun. 1996.
Vistnes et al., “Reconfigurable Address Generators for Stream-Based Computation Implemented on FPGAs,” Proceedings of the 19thIEEE International Parallel and Distributed Processing Syumposium (IPDPS 2005), 4 pages.
Amarasinghe et al., “Stream Architectures,” Architectures, Languages and Comilers for the Streaming Domain, Massachusetts Instititue of Technology, Pact Tutorial, Sep., 2003, pp. 1-49.
Amarasinghe et al., “Stream Compilers,” Architectures, Languages and Comilers for the Streaming Domain, Massachusetts Institute of Technology, Pact Tutorial, Sep., 2003, pp. 1-42.
Babb et al., “Parallelizing Applications into Silicon,” Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing machines, 1999, FCCM '99, Apr. 21-23, 1999, pp. 70-80.
Bhattacharyya et al., “Mapping DSP Applications onto Self-Timed Multiporcessors,” Conference Record of the 35th Asilomar Conference on Signals, Systems and Computers, Nov. 2001, vol. 1, pp. 441-448.
Buck, “Static Scheduling and Code Generation from Dynamic Dataflow Graphs With Integer-Valued Control Streams,” Conference Record of the 28th Asilomar Conference on Signals, Systems and Computers, Oct. 31 - Nov. 2, 1994, vol. 1, pp. 508-513.
Callahan, “Kernel Formation in Garpcc,” 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines 2003, FCCM '03, Apr. 9-11, 2003, pp. 308-309.
Callahan et al., “The Garp Architecture and C Compiler,” Computer, vol. 33, Issue 4, Apr. 2000, pp. 62-69.
Caspi et al., “A Streaming Multithreaded model,” 3rd Workshop on Media and Stream Processors (MSP-3) Dec. 2, 2001, 8 pages.
Caspi et al., “Stream Computations Organized for Reconfigurable Execution (Score): Induction and Tutorial,” Abstract, U.C. Berkley BRASS Group, Aug. 25, 2000, Version 1.0, pp. 1-31.
Chiricescu et al., “RSVP II: A Next Generation Automotive Vector Processor,” Proceedings of the IEEE Intelligent Vehicles Symposium, 2005, Jun. 6-8, 2005, pp. 563-568.
Ebeling et al., “RaPiD - Reconfigurable Pipelined Datapath,” The 6th International Workshop on Field-Programmable logic and Applications, 1996.
Erez “Stream Architectures - Efficiency and Programmability,” Proceedings of the International Symposium on System-on-Chip, Nov. 16-18, 2004, p. 41.
Erez et al., “Merrimac - Supercomputing with Stream, Extended Abstract for GP2 Poster Session,” Stanford University, Stanford CA, 1 page.
Goldstein et al., “PipeRench: a Reconfigurable Architecture and Compiler,” Computer, vol. 33, Issue 4, Apr. 2000, pp. 70-77.
Govindarajan et al., “A Novel Framework for Multi-Rate Scheduling in DSP Applications,” Proceedings of the International Conference on Application-Specific Array Processors, Oct. 25-27, 1993, pp. 77-88.
Greb et al., “GPU-ABiSort: Optimal Parallel Sorting on Stream Architectures,” 20th International Parallel and Distributed Processing Symposium, IPDPS, Apr. 25-29, 2006, 10 pages.
Jayasena et al., “Streams and Vectors: A Memory System Perspective,” Abstract, Computer Systems Laboratory, Stanford university, Stanford, CA, pp. 1-10.
Kapasi et al., “Programmable Stream Processors,” Computer, vol. 36, Issue 8, Aug. 2003, pp. 54-62.
Kapasi et al, “The Imagine Stream Processor,” Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, Sep. 16-18, 2002, 282-288.
Kathail et al., “Pico: Automatically Designing Custom Computers,” Computers, vol. 35, Issue 9, Sep. 2002, pp. 39-47.
Li et al., “Hardware-Software Co-Design of Embedded Reconfigurable Architectures,” Proceedings of the 37th Design Automation Conference 2000, Jun. 5-9, 2000, pp. 507-512.
McKEE et al., “Dynamic Access Ordering for Streamed Computations,” IEEE Transactions on Computers, vol. 49, No. 11, Nov. 2000, pp. 1255-1271.
Ranganathan et al., “Reconfigurable Caches and their Applications to Media Processing,” IEEE 2000, Proceedings of the 27th International Symposium on Computer Architecture, 2000, pp. 214-224.
Serebrin et al., “A

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