Automatic generation of correct minimal clocking constraints...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C703S016000

Reexamination Certificate

active

11151043

ABSTRACT:
A electronic design automation tool, apparatus, method, and program product by which design requirements for an intended semiconductor product and the resource definitions of a semiconductor platform are input. From the design requirements and the resource definitions, parameters specific to clocking are derived, e.g., clock property information, clock domain crossing information, and clock relationship specification. The tool and method embodied therein validates the clocking parameters of the design requirements with the resource definitions and invokes errors if the parameters are not realizable. Once the desired clocking parameters are consistent with the actual clocking parameters, correct physical optimization constraints and timing constraints are generated for the clocks. An iterative process can achieve correct and minimal clocking constraints.

REFERENCES:
patent: 5649176 (1997-07-01), Selvidge et al.
patent: 6421818 (2002-07-01), Dupenloup et al.
patent: 6442739 (2002-08-01), Palermo et al.
patent: 6536024 (2003-03-01), Hathaway
patent: 6754877 (2004-06-01), Srinivasan
patent: 6785873 (2004-08-01), Tseng
patent: 6836877 (2004-12-01), Dupenloup
patent: 6910201 (2005-06-01), Byrn et al.
patent: 7003741 (2006-02-01), Srinivasan
patent: 7134062 (2006-11-01), Yan
patent: 7187741 (2007-03-01), Pontius et al.
patent: 7296246 (2007-11-01), Kuehlmann et al.
patent: 2004/0210857 (2004-10-01), Srinivasan
patent: 2005/0198601 (2005-09-01), Kuang et al.
patent: 2006/0117274 (2006-06-01), Tseng et al.
patent: 2006/0123370 (2006-06-01), Vergara-Escobar
patent: 2006/0230373 (2006-10-01), Dirks et al.
Littlefield, Jay and Sundaresan, Subash, Formal Approach eases multiple clock design, PlanetAnalog.com, May 20, 2004, 7 pages, http://www.planetanalog.com/printableArticle.jhtml?articleID+20900163.
Murphy, Bernard, Reducing false errors in clock-domain crossing analysis, PlanetAnalog.com, Jan. 17, 2005, 6 pages, http://www.planetanalog.com/showArticle.jhtml?articleID=57701580.

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