Automatic extension of clock gating technique to...

Details Automatic extension of clock gating technique to... Automatic extension of clock gating technique to...

2008-01-29

2008-01-29

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S095000, C326S096000

Reexamination Certificate

active

07323909

ABSTRACT:
A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.

REFERENCES:
patent: 6586982 (2003-07-01), Furusawa et al.
patent: 7102382 (2006-09-01), Drenth et al.

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