Automatic engineering change order methodology

Details Automatic engineering change order methodology Automatic engineering change order methodology

1999-03-03

2002-09-17

Niebling, John F. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06453454

ABSTRACT:

FIELD OF THE INVENTION
The invention generally relates to computer-aided design techniques for large-scale integrated circuits, and more particularly relates to configuring gate array cells for Engineering Change Order (ECO).
BACKGROUND OF THE INVENTION
Rapid advances of very large-scale integrated circuit (VLSI) technologies have made design of integrated circuits increasingly complex. Computer-Aided Design (CAD) has become a necessity to speed up and improve the quality of VLSI design. In designing a VLSI circuit, logic design engineers typically implement the VLSI circuit in a Hardware Description Language (HDL) specification using a high-level CAD software such as Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), Verilog, etc. Alternatively, the VLSI circuit may be implemented by schematic design. Next, the HDL. specification is synthesized into a netlist which is essentially a data file consisting of all the logic gates required for the VLSI circuit. Such synthesis is typically carried out using a CAD compiler such as those from Synopsys Corporation of San Jose, Calif. The above steps make up the logic design phase.
Using the synthesized netlist, a computer layout of the VLSI circuit can be created. Generally, the computer layout is created by arranging a number of individual blocks or “logic cells” according to predetermined schematics. The functionality and design of individual logic cells may be predetermined and stored on a computer system as a standardized design. Such design techniques can save considerable time, as it is no longer necessary for an integrated circuit designer to custom design each individual gate and transistor in an integrated circuit. Rather, the circuit designer breaks down a new circuit design into a number of known (or new) cell designs and then combines these cells together to generate a circuit design, which performs a desired function. Each of the logic cells contains a number of terminals for implementing into the integrated circuit. These logic cells are commercially available.
Commercial “place-and-route” CAD tools, such as Cell
3
™ or Silicon Ensemble™ from Cadence Design Systems, Inc., of San Jose, Calif., are then utilized to generate the physical layout of the VLSI circuit. More particularly, place-and-route CAD programs are used 1) to arrange logic cells and other elements to optimize their interconnections and the overall surface area and 2) to define the routing region and to select channels to connect the logic cells and elements. To perform the tasks mentioned above, a place-and-route CAD tool requires as input a predetermined number (including reserves) of predefined logic cell types (e.g., AND-gate, OR-gate, flip-flop, etc.). Information related to the logic cells along with the required terminal connections are provided to the place-and-route CAD tool in the netlist which can be preserved and updated at subsequent times as needed to reflect changes. In response, the place-and-route CAD tool outputs a physical layout.
Using the computer layout generated as a blueprint, a number of base, contact, and metal layers defining the elements and interconnections of the VLSI circuit are created in silicon through a combination of semiconductor processes namely depositing, masking, and etching. When combined, these layers form the VLSI circuit. Depending on the complexity of the application specific VLSI circuit, each circuit may involve multiple base layers, multiple contact, and multiple metal layers. The above steps make up the physical design phase.
Following the generation of a physical layout, for various reasons including design changes, modifications are subsequently required to delete as well as add logic elements and interconnections from the VLSI circuit. When this occurs, an engineering change order (ECO) is generated to document the desired changes. To implement these ECO changes, extra logic cells of different types are incorporated in the original netlist as reserves. Under one conventional ECO methodology, the desired changes are incorporated by manually selecting spared logic cells and making the necessary connections to these selected spared cells to provide the desired logic functions. Such a conventional manual ECO methodology is therefore carried out entirely during the physical design phase. Given the increasing complexity of VLSI circuits, the existing obstacles, and the space constraints in the layout, this manual ECO methodology involves painful and time consuming task to identify the extra logic cells and provide the proper wiring to properly connect the added cells. As a result, the turn-around time to incorporate the desired ECO changes is generally high.
Under another conventional ECO methodology, the ECO changes are automatically incorporated entirely during the logic design phase. More particularly, an ECO compiler is used for implementation of ECO's. The ECO compiler compares the logic designer's new HDL specification (i.e., with the desired ECO changes) to the old HDL specification to determine the extent of logical change. The ECO compiler then changes the original synthesized netlist as required to conform to the new HDL specification. The modified netlist inherits has much of the original netlist as possible including cell instance and net names. The modified netlist is then transferred to the physical design environment in which incremental place and route is performed. The main tasks in this conventional ECO methodology involve equivalence checking to identify equivalent logic regions for reuse, ECO synthesis to maximally reuse old logic during resynthesis, and spare cell mapping to map new logic functions onto reserved spare standard cells.
While this conventional automatic ECO methodology generally improves the time to market compared to the manual ECO methodology discussed above, it suffers from inflexibility as a limitation. Under this conventional automatic ECO methodology, reserved/spare standard logic cells of different and predefined types are already included as reserves when the original netlist is synthesized in case ECO changes are required subsequently. Additionally, due to limitations inherent in the software environment (e.g., capability to handle a limited number of variables), the place-and-route CAD tool requires that these extra logic cells be of predefined types and numbers. Because the types of the logic cells are predefined as AND gates, OR gates, flip-flops, etc., modifications are limited to changing the logic cells connectivity. Such inflexibility may cause disastrous consequences. For example, in adding logic elements as required under an ECO, a logic cell of a certain type may not be available for implementing a desired function. As a result, either the desired function must be deleted or the process of generating a new computer layout with the desired logic cells must be restarted thereby resulting in the rejection of the VLSI silicon manufactured. These options are not desirable for reasons including delays, costs, and others. Moreover, it may not be possible to meet the ECO performance requirements because the performance of the reserved standard logic cells becomes fixed at the time they are selected and implemented. Furthermore, because synthesized designs are very optimized in terms of gate use, it is difficult to trace the gate level netlist and/or to locate spare logic cells after synthesis which may result in a time-to-market delay.
As semiconductor processing technology advances into deep sub-microns territory (e.g., 0.25&mgr;, 0.18&mgr;, and smaller), logic cells are packed into increasingly tighter space. Accordingly, there is less space available to reserve logic cells for ECO purposes. For this reason, it is more important than ever to conserve and more fully utilize all the spare logic cells reserved for ECO. Failing to do so, more silicon rejections and consequently more tape-outs are likely to result, which may lead to inefficiency, delays, and increased costs. Moreover, it is desirable that the netlist be easily tr

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