Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-12-03
2004-03-02
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S202000, C711S211000, C710S316000, C712S300000
Reexamination Certificate
active
06701418
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is sensing inverted, rearranged address or data lines in the connection between a data processor and memory.
BACKGROUND OF THE INVENTION
Typical computing systems include memory either on the main system board or installed in sockets. Data bits wired between the host central processing unit (CPU) and chipset (first system) and the memory are commonly rearranged on the first system's printed circuit board. This is illustrated in FIG.
1
. Rearranging data lines is usually of no consequence since data written will undergo the inverse mapping when retrieved. However, for a device to share data in memory with the first system without using the same data lines, this data line reordering must be recognized and remedied. Also, because of the multiplexed row/column addressing scheme used by dynamic random access memories (DRAMs), for example, and the need to support DRAMs with different row/column sizes, first systems commonly must rearrange the address bits of the memory address. For a device to share memory with the first system and maintain a contiguous address map without using the same address lines, this address line reordering must be recognized and remedied. In addition, some motherboards invert certain address bits, and in principle could invert some or all data bits as well. Likewise, for a device to share memory with the first system effectively without using the same address lines, this inversion of address lines must be recognized and remedied. Similarly inversion of any data lines in principle could be detected and remedied.
SUMMARY OF THE INVENTION
In many systems using standard memory, for example DRAM, certain manipulations including rearranging and inversion of address lines and data lines are employed. The result of these manipulations is that the data becomes unrecognizable and/or not locatable without detailed knowledge of the address line and data line manipulation, making the stored data unusable when accessed through alternative address lines and/or data lines.
To remedy this situation, the present invention determines the exact nature of rearrangements and/or inversions of address lines and/or data lines, and makes corresponding corrections.
One example application is a processor enhanced memory module (PEMM), which is compatible with both a Joint Electron Device Engineering Council (JEDEC) standard and an Electronics Industries Association of Japan (EIAJ) standard. This device plugs into a standard dual in-line memory module (DIMM) slot on a standard personal computer (PC), but on the computer printed circuit board, the processor uses separate address and data lines from the host PC.
Without the capability of the current invention, this device could not be used unless the address line and data line manipulations were known a priori and compensated for in a fixed way. However, by using the technique described here, the PEMM can be used in a PC where the address line and data line manipulations are not known a priori, and the compensation is not fixed before hand.
This invention should prove useful in many situations where a storage device is accessed through more than one set of address and/or data lines and the exact manipulations of one (or more) sets of storage lines is unknown beforehand.
REFERENCES:
patent: 4740972 (1988-04-01), Rutherford, Jr.
patent: 5095525 (1992-03-01), Almgren et al.
patent: 5987581 (1999-11-01), Nale
patent: 6327651 (2001-12-01), Dubey et al.
Heape Judd E.
Poletto Christopher J.
Trautmann Steven
Brady III W. James
Gossage Glenn
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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