Automatic design method including automatic processing for...

Details Automatic design method including automatic processing for... Automatic design method including automatic processing for...

2006-06-01

2008-10-28

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07444611

ABSTRACT:
In an area extracting step, areas interposed among tower post rows adjacent to one another, and rectangular areas interposed among the tower post rows and pads at outer peripheral portions of a chip are respectively extracted as areas in which equalization of wire spacings is performed. Areas interposed among tower post columns adjacent to one another, and rectangular areas interposed among the tower post columns and pads at outer peripheral portions of the chip are also respectively extracted as areas in which equalization of wire spacings is performed. A wiring extracting step for extracting wirings from an equalized area, a wire spacing equalizing step for extracting line segments extending in a longitudinal direction of the equalized area from the extracted wirings and shifting the same to thereby equalize spacing these line segments, and an expanding/contracting step for extracting and expanding/contracting line segments other than those extending in a longitudinal direction to thereby restore the states of connections of the line segments to the longitudinally-extending line segments.

REFERENCES:
patent: 6202195 (2001-03-01), Tanaka et al.
patent: 7013253 (2006-03-01), Cong et al.
patent: 2006/0117290 (2006-06-01), Katagiri
patent: 5-250441 (1993-09-01), None
patent: 7-271836 (1995-10-01), None
patent: 2000-35986 (2000-02-01), None
patent: 2000-100955 (2000-04-01), None
patent: 2002-83006 (2002-03-01), None

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