Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-04-18
2003-08-19
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S230060
Reexamination Certificate
active
06608797
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) memory devices and those devices incorporating embedded memory. More particularly, the present invention relates to an automatic delay technique for early “read” and “write” memory access operations in synchronous dynamic random access memory (“SDRAM”) devices and those ICs employing embedded SDRAM arrays.
“Read” and “write” commands can only be given to dynamic random access memory (“DRAM”) devices after the row address has been decoded, the appropriate word line (“WL”) selected, the proper bit line (“BL”) signal amplified and the applicable sense amplifier (“SA”) latched. The period of time between the bank select and read/write command assertion is commonly referred to as t
RCD
, or the row address strobe (“/RAS”) to column address strobe (“/CAS”) delay.
If a DRAM “read” or “write” command is allowed to occur too early, data can be corrupted by what is generally termed a sense amplifier “disturb”. This “disturb” can cause an operational failure through the premature “read” of a selected column address, with a resultant failure in correctly reading that address. Alternatively, if a “write” is allowed to occur too early, adjacent columns can fail due to the act of writing to a particular column before the sense amplifiers have had time to latch their data as a consequence of capacitive coupling to those adjacent columns.
In this regard, circuits have been developed for asynchronous (or non-clocked) DRAMs such as extended data out (“EDO”) and fast page mode (“FPM”) DRAMs wherein the column address strobe signal may be asserted early and the read/write and address information latched on the falling edge of the /CAS signal. Internally, a clock or other timer is used to “hold off” the column select and data information until the sense amplifier has been latched. This effectively prevents the previously mentioned “disturb” condition.
On the other hand, in synchronous (or clocked) DRAMs, double data rate (“DDR”) SDRAMs and most embedded DRAMs, no analogous technique has been employed and an early /CAS has not been permitted with the external column address and data information having to equal the device's internal set-up requirements in order to prevent any array or sense amplifier “disturbs”. Due to the nature of a clocked DRAM (or SDRAM), commands can be given only once per clock period. This quantizing effect raises the importance of the present invention since there may be cases with prior art SDRAMs where the /RAS to /CAS delay (t
RCD
) specification is just barely missed and the user is force to wait for an entire clock period to start a “read” or “write” operation.
SUMMARY OF THE INVENTION
In accordance with the technique of the present invention disclosed herein, a circuit and method which controls the internal column select (“Yi”) and data signals is provided in conjunction with a synchronous DRAM array such that the /CAS signal is allowed to go “active” in advance of that otherwise possible in conjunction with conventional SDRAM devices and other ICs having embedded SDRAM arrays.
In an exemplary embodiment disclosed herein, a system for implementing the technique of the present invention functions to delay the column select signal “Yi” (either the “read” column select signal “Y
Ri
” or the “write” column select signal “Y
Wi
”) until either of the pre-decoded column address signals “CA
210
” (either the corresponding pre-decoded “read” column address signal “CA
210
R” or the pre-decoded “write” column address signal “CA
210
W”) or the column clock signal “PHIYB” (either the corresponding column clock “read” signal “PHIYBR” or the column clock “write” signal “PHIYBW”) is valid, whichever occurs later. Functionally, the PHIYB signal is delayed by the clock “CLK” or select “SEL” (either the “read” select signal “RSEL” or the “write” select signal “WSEL”), whichever is later. For the “write” circuitry disclosed herein, the array select “write” signal “ASELW” output from the array select circuit is used, which signal goes “valid” after the sensing begins. For the “read” circuitry disclosed herein, the array signal “read” signal “ASELR” is used, which signal goes “valid” a fixed delay after the sensing begins. This allows the sense amplifier latch nodes to separate before Y
Ri
goes “valid” to ensure a fast read access time “t
AC
”.
Particularly disclosed herein is a method for effectuating an access operation in a synchronous dynamic random access memory array arranged in rows and columns. The method comprises the steps of: awaiting an indication of a valid state of a pre-decoded column address signal for the access operation; also awaiting an indication of a valid state of a column clock signal and delaying a column select signal for the access operation until the later of a valid state of the pre-decoded column address signal or the column clock signal. In a more detailed implementation, the method further comprises the steps of: awaiting an indication of a valid state of an array select signal for the access operation; further awaiting assertion of a clock signal and delaying the indication of a valid state of the column clock signal until the later of a valid state of the array select signal or the clock signal.
When the access operation is a “write” operation, the method may further comprise the steps of: detecting a sense amplifier enable signal to the memory array and indicating the valid state of the array select signal upon detection of the sense amplifier enable signal. When the access operation is a “read” operation, the method may further comprise the steps of: detecting a sense amplifier enable signal to the memory array and indicating the valid state of the array select signal a predetermined time period following detection of the sense amplifier enable signal.
Also disclosed herein is an integrated circuit device including a circuit for controlling a column select signal in a synchronous dynamic random access memory array. The circuit comprises: an array select circuit for receiving a sense amplifier enable signal and providing a first array select signal in response thereto; a first column clock circuit for receiving the first array select signal, a first column address signal and a clock signal with the first column clock circuit providing a first column clock signal in response thereto and a first access operation column decoder circuit for receiving the first column clock signal and a first pre-decoded column address signal and providing a first column select signal in response thereto.
In a more detailed implementation the circuit may comprise: a second column clock circuit for receiving a second array select signal from the array select circuit, a second column address signal and the clock signal with the second column clock circuit providing a second column clock signal in response thereto. A second access operation column decoder circuit is provided for receiving the second column clock signal and a second pre-decoded column address signal and providing a second column select signal in response thereto.
REFERENCES:
patent: 6163498 (2000-12-01), Moon
Hardee Kim C.
Jones, Jr. Oscar Frederick
Parris Michael C.
Hogan & Hartson LLP
Kubida William J.
Meza Peter J.
Nguyen Tan T.
United Memories Inc.
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