Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-06
2003-04-08
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06546531
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates to an automated approach for inserting delay elements into complex, high performance VLSI circuits to address hold time problems; and more particularly to development of an algorithm and CAD solution to insert delay elements
2. Description of the Related Art
A hold time problem occurs in synchronous circuits (where operations of the circuit elements are synchronized with respect to a common timing signal, called “clock”), when the data to be registered in a storage element (referred to herein as a “flop”), when clocked, does not remain stable for at least a “holdtime” interval for the flop. The holdtime of a flop arises from the non-zero circuit delay associated with flow of data from the clock input of the flop to the point of data storage within the flop.
Hold time problems in VLSI circuits lead to incorrect data storage in a storage element or flop. The term “flop” often refers to a flip-flop, a typical circuit storage element. Incorrect data storage is likely to occur in synchronous circuits that are synchronized during operation to the clocks driving the elements in the circuits. In particular, a hold time problem occurs when data is stored in a flop after the flop has been clocked, without providing a sufficient hold time for the data. When the data is registered in a flop after clocking, the data does not remain stable for at least a time equal to what is termed the required “hold time” of a flop. As discussed in the following in connection with
FIG. 2A
, one flop can hold data sent by another flop. That is, a source flop can send data to a destination flop, in successive circuit cycles. However, before the destination flop can hold data sent from a source flop in a previous cycle, data from the source flop in the current cycle may reach the same destination flop and change the value held in the destination flop, because of speed of transport along the paths between the source flop and the destination flop. Accordingly, functional failure can occur. Due to the nature of the construction of such storage elements, the occurrence of hold time problems is common during design processes for electric circuits implemented in very large scale integration of semiconductor chips.
It is desirable to eliminate functional failures stemming from hold time problems. Industry standard computer aided design (CAD) tools are known that address hold time problems. However, such tools do not take into account the serious side effects of hold time problems. In particular, solving the delay problem in a certain path by inserting a delay element may cause an excessive cycle time delay to occur in another path, which detrimentally affects overall circuit performance by further limiting the maximum frequency response of that portion of the circuit. Accordingly, it is desirable that insertion of appropriate time delay values be done at appropriate points in hold time paths, to avoid compromising performance from a frequency perspective. It is unacceptable to insert a time delay element in a path experiencing a hold time problem without considering possible detrimental cycle time consequences elsewhere.
It is further desirable to eliminate the technical problems relating to hold time dysfunctionalities during the design of semiconductor chips involved in VLSI development, construction, and fabrication.
SUMMARY OF THE INVENTION
According to the present invention, an algorithm compensates for the limitations of standard CAD tools and hence reduces design convergence time. In particular, all the paths not meeting the hold time requirements are collected in a list or table. Next, an arbitrary storage element in a selected signal path that has a hold time problem is evaluated for time delay correction by insertion of a delay element immediately preceding the selected storage element. However, if such a proposed insertion has detrimental cycle time consequences for another path involving this element, detrimentally affecting circuit speed or maximum frequency response, for example, the proposed insertion is not implemented. Instead, another path or logic gate is considered for possible insertion of a delay element immediately preceding the selected storage element in a local span of the path under evaluation. By evaluating the successive paths in a recursive fashion, the appropriate points in a circuit path are automatically selected for insertion of delay elements in a global fashion. Further, particular time delay elements are selected with appropriate delay values from a library of delay element values, to ensure that the delay selected has a margin greater than the delay required to solve the local hold time problem without detrimental global consequences within the circuit under design.
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Greenley Dale R.
Quach Le
Varadadesikan Lakshminarasimhan
Martine & Penilla LLP
Siek Vuthe
Sun Microsystems Inc.
Tat Binh C.
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