Automatic defect source classification

Details Automatic defect source classification Automatic defect source classification

1999-07-12

2003-01-14

Smith, Matthew (Department: 2785)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C438S014000

Reexamination Certificate

active

06507933

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to quality control in the field of integrated circuit wafer manufacturing and testing.
2. Description of the Related Art
Integrated circuit manufacturing and testing requires a high degree of quality control. An integrated circuit (IC) is a miniature electric circuit composed of hundreds to tens of millions of discrete electronic circuit elements (e.g., transistors, resistors, capacitors, or inductors). Multiple ICs are manufactured, or formed, on semiconductor wafers (also known as integrated circuit wafers), through a series of oxidations, implants, controlled deposition of materials, and selective removal of materials. Manufacturing integrated circuit wafers typically requires upwards of between two hundred and four hundred discrete manufacturing steps.
Once the manufacturing process is complete, a wafer will be divided into individual die (or chips). Each functional die will be sold as an individual IC. The quality of the manufacturing process is measured by percent yield (percent of functioning die divided by total possible die per wafer). One of the main causes of reduced yield is particle defects introduced during the manufacturing process.
In order to maintain high yields, semiconductor manufactures use two approaches to monitor defect levels (number of defects at a manufacturing step) in the manufacturing process. The first approach is to inspect product wafers at multiple steps in the manufacturing process. The second approach is to use short loop monitors on key pieces of process equipment. Short loop monitors are test wafers that are processed through a few process steps. There are multiple types of short loop monitors that are used in different areas of the manufacturing process, and on different process equipment. The advantage of short loop monitors are their simplicity, high sensitivity to defects, and low jeopardy for use on suspect process equipment. The disadvantage is that they are expensive. The advantages of product wafer inspection are no added test wafer cost, and sensitivity to integration defects. The disadvantage is reduced sensitivity to defects caused by process variation inherent in semiconductor manufacturing, and the inability to determine the source of the defects.
In order to ensure that the integrated circuit wafers are correctly formed, tight quality control is needed. One form of quality control is to ensure that one or more production tools (a production tool is a term of art meaning a piece of equipment utilized as a tool to produce a semiconductor wafer) are functioning within tolerances. One way in which this is done in the art is that defect levels of both short loop monitors and product inspectioning are monitored by statistical process control (SPC). In the event of SPC failure, the product or short loop must be dispositioned.
In SPC, a wafer inspection tool inspects an integrated circuit wafer and creates a defect table listing noted defects on the inspected integrated circuit wafer. Thereafter, defects from the integrated circuit wafer's defect table (a descriptive listing of defects on the integrated circuit wafer) are compared to an SPC metric. If the comparison finds the integrated circuit wafer within tolerances, no action is taken. However, if the comparison with the SPC metric fails, the product or short loop must be dispositioned. The product or short loop is dispositioned via a process known in the art as “dispositioning.”
Dispositioning, as that term is used within the art, generally entails a human (a “dispositioner”) doing the following: (1) examining a pictographic representation of defects (a “defect map”) in a completely or partially formed integrated circuit wafer; (2) determining whether a pattern of defects on a defect map represents significant defects in the manufacture of the completely or partially formed integrated circuit wafer; (3) if a determination is made that the wafer does not contain significant defects, allowing the production equipment to run unimpeded; and (4) if a determination is made that the defect map of the wafer represents significant defects in the manufacture of the wafer, determining one or more likely “causes” of the significant defects, where the determination of the “cause” encompasses both (a) where the defect occurred (e.g., the most likely production tool at which the defects occurred) and (b) why the defect occurred (e.g., bad materials used at/by a production tool, a process tool needs to be cleaned, or a mechanical failure in the process tool is producing defects).
Dispositioning is a very important aspect of integrated circuit wafer manufacturer quality control. Dispositioners have the ability to slow down or stop the production process. Dispositioners also have the ability to allow the production process to run unimpeded. It is therefore important that dispositioning be done with as much precision and accuracy as is possible since dispositioners essentially control a significant aspect of the production process.
There are several problems associated with dispositioning, as dispositioning is performed in the art. A few of those problems are as follows. First, it takes roughly 6 months to 2 years to adequately train a human to do dispositioning. This training typically involves teaching the prospective dispositioner to recognize certain visual patterns (known in the art as “defect signatures”) in defect maps, and associate those certain patterns with specific “causes” of the defects within the production process of the integrated circuit wafers. Second, being human, dispositioners are tremendously variable, with some being markedly better than others. Third, what the dispositioners are taught is not quantitative but qualitative—the dispositioners are taught to associate “causes” with visual patterns in the defect maps—and thus there is the associated human variability in visual perception and interpretation. Fourth, dispositioners, being human, are prone to human error, illness, lack of attention, etc. Fifth, when a change is made in a production process, human dispositioners often have difficulty in responding to the change.
It is therefore apparent that a need exists in the art for a method and system which will automatically perform the functions currently performed by the human dispositioners, such that the training, errors, and variability associated with the human dispositioners can be substantially avoided.
SUMMARY OF THE INVENTION
A method and system have been invented which will automatically perform the functions currently performed by the human dispositioners, such that the training, errors, and variability associated with the human dispositioners can be substantially avoided. The method and system quantitativize
1
a qualitative integrated circuit wafer defect signature. In response to the quantitativized wafer fabrication defect signature, the method and system identify at least one cause of the defect signature.
1
As used herein, the term “quantitativize” (quantitative+ize suffix) is used to describe the operation of making quantitative something that is qualitative. Furthermore, as used in this application, the terms quantitative+ed suffix, quantitative+ization suffix, and quantitative+izing suffix are used to indicate qualitative things that have been made quantitative, the operation of making something qualitative quantitative, and the action of making something qualitative quantitative, respectively.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.


REFERENCES:
patent: 5240866 (1993-08-01), Friedman et al.
patent: 5539752 (1996-07-01), Berezin et al.
patent: 5859698 (19

Affiliated with

Also associated with

Rating

Automatic defect source classification does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automatic defect source classification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic defect source classification will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3049448