Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
1999-06-30
2002-10-08
Tran, Phuoc (Department: 2621)
Image analysis
Applications
Manufacturing or product inspection
C382S145000, C382S144000, C382S194000, C382S192000, C382S286000, C382S298000
Reexamination Certificate
active
06463171
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices. More specifically, this invention relates to the manufacture and the detection and classification of defects during the manufacture of high performance semiconductor devices. Even more specifically, this invention relates to the manufacture and the detection and classification of defects during the manufacture of high performance semiconductor devices utilizing an automatic defect resizing tool.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits being manufactured. Part of the increase in performance and in the reduction in cost of the semiconductor integrated circuits being manufactured is accomplished by shrinking the semiconductor device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the manufacturing yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects during the manufacturing process. The number of good chips obtained from a wafer determines the yield and, as can be appreciated, chips that are discarded because of a defect or defects increases the cost of the remaining usable chips because the cost of manufacturing is amortized over the remaining usable chips.
A single semiconductor chip requires numerous processing steps during its manufacture. These steps include processing steps such as deposition of materials, implantation of ions, oxidation, etching, metallization and wet chemical cleaning. Typically, these processing steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during each of the processing steps. The optimization of each of these processing steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of semiconductor chips in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of the resulting integrated circuits. A major part of the analysis process is to capture (detect) defects, properly classify the defects, and to analyze the defects completely to determine what caused the defects and to eliminate or avoid the cause of the defects.
In order to be able to quickly resolve process or equipment issues in the manufacture of semiconductor products, a great deal of time, effort and money is being expended by semiconductor manufacturers to capture and classify silicon based defects. Once a defect is caught and properly described and classified, work can begin to resolve the cause of the defect and to eliminate or avoid the cause of the defect. One of the biggest problems that faced semiconductor manufacturers was the inability of human inspectors to uniformly classify defects consistently and without error. This problem was solved by the development of Automatic Defect Classification (ADC) systems.
One ADC system for automatically classifying defects includes the following methodological sequence. View an image of a defect in an ADC Review Tool and assign values to elemental descriptor terms called predicates that are general descriptors such as roundness, brightness, color, hue, graininess, etc. Assign a classification code to the defect based upon the values of all the predicates. A typical ADC system can have 40 or more quantifiable qualities and properties that are considered predicates. Each predicate can have a specified range of values and a typical predicate can have a value assigned to it between 1 and 256. A value of 1 indicates that none of the value is present and a value of 256 indicates that the quality represented by the predicate is ideal. For example, a straight line would have a value of for the predicate indicating roundness, whereas a perfect circle would have a value of 256 for the same predicate.
A great enabler in the field of defect capture and analysis and the use of ADC systems has been the creation of Defect Management Systems (DMS). These DMS systems relationally associate defects with product/layer/wafer locations allowing the recapture of these defects on various analytical tools, as well as yield or trend analysis with other process related events. Increasingly, analysis tools, such as FIB (fixed ion beam) and SEM/EDS (scanning electron microscopes/energy dispersive spectroscopy) tools have been used in the manufacturing environment and images generated by these tools are routinely appended to these defects as image files. This has enhanced the ability of yield or process experts to quickly view images and/or spectra that would normally be kept in a folder that is retrievable manually.
The ADC system determines the classification code for each defect from the combination of all the predicate values assigned to the defect. The goal of an ADC system is to be able to uniquely describe all the defect types in such a manner that a single classification code can be assigned to a defect which is differentiated from all other defect types. This is accomplished by a system administrator who programs an artificial intelligence system to recognize various combinations and permutations of the 40 or more predicates to assign the same classification code to the same type of defect. This would result in a highly significant statistical confidence in the probability that the defect and all other defects of the same type or class will always be assigned the same classification code by the ADC system. These predicate values from the ADC system are stored in a database by the DMS.
The information in the DMS controlled database is retrievable for various purposes, including further processing, analysis, off-line viewing, and charting. The properly classified defects are then viewed via Pareto charts to determine, on a macro level, the current level of defectivity for various defect types.
As the dimensions of the device geometry continue to shrink, it is becoming increasingly important to ascertain an accurate defect size associated with a specific type of defect. The accurate sizing information is critical for many of the post analysis tools for the determination of parametrics that include critical area, kill ratio, and defect to tool matching.
Currently, wafers are scanned at the current level by optical or laser-scanning tools that perform such tasks including detecting defects, noting x-y location, and estimating size. Although a great deal of faith is placed on the estimated size of defects, it is notoriously inaccurate and can and has lead to erroneous conclusions. Current methods of sizing include returning sizing values as a function of greatest x-chord, or x-max multiplied by y-max, or as a constant multiplied by scattered light intensity. Analysts are very hesitant to trust the results from the present methods of determining sizes of defects.
Therefore, what is needed is a method to accurately determine the size of defects that can be used for post-analysis work.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are attained by using an automatic defect resizing tool.
In accordance with an aspect of the invention, a semiconductor wafer production lot is sent through a manufacturing process, a first layer of the wafer lot is processed, a selected inspection wafer is placed in a scan tool, defect location information is sent to a defect management system, which sends the defect location information to an automatic defect classification review tool where the automatic de
Steffan Paul J.
Yu Allen S.
Advanced Micro Devices , Inc.
Bayat Ali
Nelson H. Donald
Tran Phuoc
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