Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2001-01-12
2004-06-01
Vo, Tim (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S114000, C710S116000
Reexamination Certificate
active
06745273
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for bus arbitration generally and, more particularly, to a method for avoiding a bus deadlock through arbitration switching.
BACKGROUND OF THE INVENTION
An Advanced Microcontroller Bus Architecture (AMBA) specification defines on-chip communications standards for microcontrollers. The AMBA specification is being used worldwide by a variety of application specific integrated circuit vendors. The AMBA is being used in wireless, telecommunications, networking, office automation, and storage applications. The AMBA specification defines three busses, an Advanced High-Performance Bus (AHB), an Advanced System Bus (ASB), and an Advanced Peripheral Bus (APB).
The AHB portion of the AMBA specification provides communications between multiple masters and multiple slaves via the AHB. A bus mastership for the AHB is controlled by an arbiter using a fixed priority arbitration scheme. When a given master has the bus mastership, then the given master may initiate one or more transfers with one or more slaves. Any slave that cannot respond immediately to a transfer may issue a RETRY or a SPLIT response. The RETRY and the SPLIT responses allow the bus to be used for other purposes while the slave prepares the transfer.
The AHB specification states that the slave issuing the RETRY response (a “retry slave”) should only be involved in transfers to one master at a time. The AHB specification, however, has no provisions to enforce the one-master-at-a-time limitation. Consequently, a deadlock situation on the AHB may be created when two masters initiate overlapping transfers to one retry slave.
Consider a situation where a first master initiates a first transfer with the retry slave. While the retry slave is preparing to complete the first transfer, a second master of higher priority may obtain the bus mastership. If the second master initiates a second transfer with the retry slave, then the retry slave will present a RETRY response to the second master. The retry slave will then ignore or delay the second transfer until the first transfer is completed. However, the second master will prevent the first master from obtaining the bus mastership until the second transfer is completed. The result is a deadlock on the bus.
SUMMARY OF THE INVENTION
The present invention concerns a method for controlling arbitration that may be used for a bus. The method generally comprises the steps of (A) controlling a bus mastership for the bus using a first arbitration scheme, (B) controlling the bus mastership using a second arbitration scheme in response to a first signal indicating a delay in a transfer between a first master of a plurality of masters and a slave on the bus, and (C) controlling the bus mastership using the first arbitration scheme in response to a second signal ending the delay in the transfer between the first master and the slave.
The objects, features and advantages of the present invention include providing a method and/or architecture that may (i) prevent retry capable slaves from deadlocking a bus in a multiple-master system, (ii) avoid added complexity to the retry capable slaves, and/or (iii) provide a fixed priority arbitration scheme for the bus under most practical conditions.
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AMBA™ Specification (Rev. 2.0), 1999, 1-1 through 6-38.
Gehman Judy M.
Holm Jeffrey J.
Waasdorp Karla K.
Wiita Richard D.
LSI Logic Corporation
Maiorana PC Christopher P.
Vo Tim
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