Automatic cell placement method

Details Automatic cell placement method Automatic cell placement method

2000-10-03

2003-05-06

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06560760

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic cell placement method in which cells to be arranged in a semiconductor integrated circuit are automatically placed so as to shorten a total length of signal wires connecting the cells with each other.
2. Description of Related Art
As the number of cells (or electronic circuits) arranged in a semiconductor integrated circuit is increased, the influence of signal delay caused in signal wires on the circuits becomes important. In cases where intervals of signal wires connecting the cells with each other become shorter than 0.25 gm, the signal delay caused in signal wires becomes longer than the signal delay caused in transistors. Because the signal delay caused in a signal wire is in proportion to a signal wire length squared, it is required to shorten lengths of signal wires for the purpose of decreasing the signal delay caused in the signal wires.
In a conventional automatic cell placement and route method used for the manufacturing of a semiconductor integrated circuit, Min-Cut Placement (Melvin A. Breuer, “Min-Cut Placement”, Journal of Design Automation & Fault Tolerant Computing, Vol.1, No.4, pp.343-362, October 1977) is widely used in a cell placing process as a conventional automatic cell placement method.
In the Min-Cut Placement, a placement area of a plurality of cells, which are connected with each other through signal wires, is repeatedly divided into two parts along a cut line. In this case, each of the cells is placed in one of two divided placement areas to minimize the number of signal wires crossing the cut line. More precisely, in cases where two or more cells are placed in each of the two divided placement areas, each divided placement area is again divided into two parts along another cut line. In cases where two or more cells are placed in one of the two divided placement areas and only one cell is placed in the other divided placement area, only the divided placement area having two or more cells is again divided into two parts along another cut line. Also, in cases where only one cell is placed in each of the two divided placement areas, the division of each divided placement area is not performed any more. That is, the division of the divided placement area is repeated until the number of cells placed in the divided placement area reaches 1, and the placement area of the cells is finally divided into a plurality of minimum placement areas respectively having one cell.
Therefore, in the Min-Cut Placement, in cases where the number of signal wires connecting a plurality of particular cells with each other is large, the minimum placement areas of the particular cells are closely placed. In contrast, in cases where the number of signal wires connecting a plurality of particular cells with each other is small or zero, the minimum placement areas of the particular cells are placed far from each other. Accordingly, a total length of the signal wires can be shortened.
FIG. 5A
shows a plurality of cells placed in a cell placement area, and
FIG. 5B
to
FIG. 5E
show the cell placement areas respectively divided along one cut line or a plurality of cut lines according to the Min-Cut Placement. In
FIG. 5A
to
FIG. 5E
,
101
indicates a first cell,
102
indicates a second cell,
103
indicates a third cell,
104
indicates a signal wire connecting each pair of cells with each other,
105
indicates a cell placement area,
106
indicates a minimum cell placement area obtained by repeatedly dividing the cell placement area
105
, C
101
indicates a first cut line, C
102
indicates a second cut line, C
103
indicates a third cut line, C
104
indicates a fourth cut line, C
105
indicates a fifth cut line, and C
106
indicates a sixth cut line.
As shown in
FIG. 5B
, the cell placement area
105
shown in
FIG. 5A
is divided along the cut line C
101
, the cells
101
and
102
are placed in a divided cell placement area, and the cell
103
is placed in another divided cell placement area. As shown in
FIG. 5C
, each of the cell placement areas shown in
FIG. 5B
is divided along the cut line C
102
, and the cells
101
,
102
and
103
are respectively placed in a divided cell placement area. As shown in
FIG. 5D
, each of two upper cell placement areas shown in
FIG. 5C
is divided along the cut line C
103
into two parts to place cells (not shown) in each of divided upper cell placement areas, and each of two lower cell placement areas shown in
FIG. 5C
is divided along the cut line C
104
into two parts to place cells (not shown) in each of divided lower cell placement areas. As shown in
FIG. 5E
, each of four left cell placement areas shown in
FIG. 5D
is divided along the cut line C
105
into two parts to place a cell (not shown) in each of minimum left cell placement areas
106
, and each of four right cell placement areas shown in
FIG. 5D
is divided along the cut line C
106
into two parts to place a cell (not shown) in each of minimum right cell placement areas
106
.
As is described above, in the Min-Cut Placement, because a placement area of a plurality of cells is repeatedly divided into two parts along a cut line to place only one cell in each divided placement area while minimizing the number of signal wires crossing the cut line every division, the Min-Cut Placement is useful for the manufacturing of a semiconductor integrated circuit in which a plurality of electronic circuits are arranged only on a single semiconductor chip.
However, as is disclosed in the U.S. Pat. No. 5,923,091, in cases where a semiconductor integrated circuit is manufactured by attaching two semiconductor chips to each other to make electronic circuits arranged on one semiconductor chip face electronic circuits arranged on the other semiconductor chip, because the group of electronic circuits of the semiconductor chips of the semiconductor integrated circuit is not arranged in one plane, there is a problem that the Min-Cut Placement is not appropriate for the manufacturing of the semiconductor integrated circuit in which electronic circuits arranged on one semiconductor chip face electronic circuits arranged on the other semiconductor chip. This type of semiconductor integrated circuit is described with reference to
FIG. 6A
to FIG.
6
D.
FIG. 6A
is a plan view showing a plurality of cells (or electronic circuits) arranged on a first semiconductor chip of a semiconductor integrated circuit,
FIG. 6B
is a plan view showing a plurality of cells (or electronic circuits) arranged on a second semiconductor chip of the semiconductor integrated circuit,
FIG. 6C
is a plan view showing the semiconductor integrated circuit in which the first and second semiconductor chips are attached to each other so as to make the cells of the first semiconductor chip face the cells of the second semiconductor chip, and
FIG. 6D
is a cross sectional view taken substantially along line X—X of FIG.
6
C. In
FIG. 6A
to
FIG. 6D
,
13
indicates a first semiconductor chip,
14
indicates a second semiconductor chip,
1
indicates a first cell arranged on the first semiconductor chip
13
,
2
indicates a second cell arranged on the first semiconductor chip
13
,
3
indicates a third cell arranged on the second semiconductor chip
14
,
4
indicates a fourth cell arranged on the second semiconductor chip
14
,
9
indicates an input/output pin of the first cell
1
,
10
indicates an input/output pin of the second cell
2
,
11
indicates an input/output pin of the third cell
3
,
12
indicates an input/output pin of the fourth cell
4
,
15
indicates a signal wire connecting the input/output pin
10
of the second cell
2
and the input/output pin
12
of the fourth cell
4
, and
16
indicates each of a plurality of bonding pads arranged in the peripheral area of the first semiconductor chip
13
.
As shown in
FIG. 6A
to
FIG. 6D
, the first semiconductor chip
13
, on which a first group of cells including the cells
1
and
2
is arranged, is formed, the second semiconductor chip
14
, on

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