Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-04
2003-01-07
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C257S202000, C257S698000
Reexamination Certificate
active
06505335
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic cell placement and routing method, in which cells to be arranged in a semiconductor integrated circuit are automatically placed to design a layout pattern of the cells, and a semiconductor integrated circuit in which timing considered cells automatically placed according to the automatic cell placement and routing method in the design of a layout pattern of the timing-considered cells are arranged with a timing-free-cell.
2. Description of Related Art
In cases where a plurality of timing-considered cells connected with each other on a signal path are to be arranged in a semiconductor integrated circuit on condition that an input timing of a signal input to each timing-considered cell is considered, it is required to design the layout pattern of the timing-considered cells according to timing constraints of the timing-considered cells. Therefore, in cases where the layout pattern of the timing-considered cells in the semiconductor integrated circuit is designed according to a conventional automatic cell placement and routing method (or called a place and route method) based on a timing driven layout technique, the timing constraints of the timing-considered cells are added to an automatic placement and routing tool, and a layout pattern of the timing-considered cells is designed so as to satisfy the timing constraints of the timing-considered cells.
However, in cases where a timing-free cell (for example, an asynchronous circuit), in which an input timing of a signal is not considered, is connected with the timing-considered cells on the signal path, it is impossible to design a layout pattern of the timing-considered cells and the timing-free cell according to the conventional automatic cell placement and routing method based on the timing driven layout technique while satisfying the timing constraints of the timing-considered cells.
FIG. 12
shows a plurality of cells placed on a signal path in a semiconductor integrated circuit. In
FIG. 12
,
21
indicates a timing-considered cell denoting a storing element such as a flip-flop or a latch.
22
indicates a timing-free cell in which an input timing of a signal is not considered.
23
indicates another timing-considered cell such as a combinational circuit. A signal passes through the cells
21
,
22
and
23
placed on a signal path from the left side to the right side in FIG.
12
. That is, a signal passing through the signal path is input to the first timing-considered cell
21
placed on the most left side, the first timing-considered cell
23
, the timing-free cell
22
, the second timing-considered cell
23
and the second timing-considered cell
21
placed on the most right side in that order. Each pair of cells adjacent to each other is connected with each other through a net. Each timing-considered cell has timing information indicating a timing constraint for a signal which is input to the timing-considered cell through a net. For example, a signal transmission delay time allowed for each timing-considered cell is considered within an allowable time range. Information of the set of the cells
21
,
22
and
23
and a connection relationship among the cells
21
,
22
and
23
connected with each other through nets are stored in a data base as a logical net list.
In the example of the cells
21
,
22
and
23
shown in
FIG. 12
, because a net
24
connects the first timing-considered cell
21
and a signal input terminal (not shown) and because a net
25
connects the second timing-considered cells
21
and
23
, it is required to design a layout pattern of cells
21
,
22
and
23
placed on the signal path extending from the net
24
to the net
25
according to the conventional automatic cell placement and routing method based on the timing driven layout technique while using the logical net list and the timing information of the timing-considered cells and nets.
However, because no timing information of the timing-free cell
22
is prepared, a layout pattern of cells
21
,
22
and
23
placed on the signal path from the net
24
to the net
25
cannot be designed according to the conventional automatic cell placement and routing method based on the timing driven layout technique. Therefore, it is required to manually check a signal transmission time period for each pair of timing-considered cells adjacent to each other.
As is described above, in cases where the timing-free cell having no timing information is placed on a signal path on which a plurality of timing-considered cells are placed, it becomes impossible to design a layout pattern of the timing-considered cells and the timing-free cell on the signal path according to the conventional automatic cell placement and routing method based on the timing driven layout technique, and it is required to manually design a layout pattern of the cells placed on the signal path while checking a transmission delay time of a signal for each timing-considered cell. Therefore, a design time required for the design of the layout pattern of the cells to be arranged in the semiconductor integrated circuit is lengthened, and there is a problem that a design efficiency for the design of the layout pattern of the cells is lowered.
SUMMARY OF THE INVENTION
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional automatic cell placement and routing method, an automatic cell placement and routing method in which timing-considered cells to be arranged in a semiconductor integrated circuit is automatically placed at high speed in the design of a layout pattern of the timing-considered cells according to timing constraints of the timing-considered cells even though a timing-free cell is placed with the timing-considered cells on a signal path. Also, the object of the present invention is to provide a semiconductor integrated circuit in which timing-considered cells automatically placed according to the automatic cell placement and routing method in a layout pattern design are arranged with a timing-free cell.
The object is achieved by the provision of an automatic cell placement and routing method, comprising the steps of:
preparing a logical net list of a timing-free cell, a plurality of timing-considered cells and nets, through which the timing-free cell and the timing-considered cells are connected with each other, to be arranged in a semiconductor integrated circuit;
preparing dummy pin information to specify the timing-free cell written in the logical net list and to isolate the timing-free cell from the timing-considered cells and the nets by placing dummy pins on both sides of the timing-free cell;
preparing timing information indicating timing constraints of the timing-considered cells and the nets through which the timing-considered cells are connected a with each other; and
performing an automatic layout routing for the timing-considered cells according to the logical net list, the dummy pin information and the timing information to design a layout pattern of the timing-considered cells to be arranged in the semiconductor integrated circuit.
Also, a semiconductor integrated circuit comprises:
the timing-considered cells in which an input timing of a signal is considered and which are placed on a signal path; and
the timing-free cell in which an input timing of a signal is not considered and which is placed on the signal path on which the timing-considered cells are placed, wherein the layout pattern of the timing-considered cells is designed according to the automatic cell placement and routing method.
In the above steps of the automatic cell placement and routing method and the configuration of the semiconductor integrated circuit, the timing-free cell is isolated from the timing-considered cells by placing the dummy pins on both sides of the timing-free cell. Therefore, the timing-considered cells to be arranged in the semiconductor integrated circuit can be automatically placed in the design of a layout pattern of the
Burns Doane , Swecker, Mathis LLP
Dimyan Magid Y
Mitsubishi Denki & Kabushiki Kaisha
Siek Vuthe
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