Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-09
2004-03-23
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06711726
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic cell placement and routing apparatus in which a layout of cells composing a semiconductor integrated circuit is designed not to receive an adverse influence of a cross-talk noise generated when the semiconductor integrated circuit is actually operated. Also, the present invention relates to an automatic cell placement and routing method used for the apparatus.
2. Description of Related Art
When a layout of cells composing a semiconductor integrated circuit is designed, to reduce cross-talk noise generated in the semiconductor integrated circuit, a method for widening an interval between wires adjacent to each other and/or inserting a buffer cell or an inverter cell into a wire is adopted in a conventional automatic cell placement and routing apparatus. Therefore, a capacitance between wires adjacent to each other is reduced, and the cross-talk noise is reduced.
This automatic cell placement and routing apparatus is, for example, disclosed in the Published Unexamined Japanese Patent Application No. H11-40677 (1999).
However, it is impossible to reduce a capacitance between wires adjacent to each other in a crowded cell area such as a peripheral area of a hard macro-block (for example, a mega-cell such as a read only memory (ROM) cell or a random access memory (RAM) cell and an input-output (IO) cell) in which the insertion of a buffer cell is difficult, a cell insertion inhibit area and a crowded wire area in which the widening of an interval between wires adjacent to each other is difficult. Therefore, because the above-described method is adopted in the conventional automatic cell placement and routing apparatus, there is a problem that it is impossible to reduce the cross-talk noise in the crowded cell area, the cell insertion inhibit area and the crowded wire area.
SUMMARY OF THE INVENTION
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional automatic cell placement and routing apparatus, an automatic cell placement and routing apparatus in which cross-talk noise is reduced without increasing an area of a semiconductor integrated circuit. Also, the object of the present invention is to provide an automatic cell placement and routing method used for the apparatus.
The object is achieved by the provision of an automatic cell placement and routing apparatus in which the placement of hard macro-blocks composing a semiconductor integrated circuit is designed and the routing in the semiconductor integrated circuit is designed. An automatic cell placement and routing apparatus comprises a designing unit for embedding a cross-talk noise improving cell, which has an external interface, in an internal open space of one hard macro-block and inserting the cross-talk noise improving cell into a wire of the semiconductor integrated circuit.
In the above configuration, because the cross-talk noise improving cell embedded in the hard macro-block is inserted into a wire of the semiconductor integrated circuit, the capacitance between the wire and an adjacent wire is reduced.
Accordingly, the cross-talk noise can be reduced without increasing an area of the semiconductor integrated circuit.
It is preferred that the cross-talk noise improving cell is inserted into one of wires adjacent to each other by the designing unit in cases where level transition periods of signals of the wires overlap with each other.
Accordingly, the adverse influence of the cross-talk noise can be reduced.
It is preferred that an inverter cell denoting the cross-talk noise improving cell is inserted into one of wires adjacent to each other by the designing unit in cases where level transition periods of signals of the wires overlap with each other and level transition directions of the signals differ from each other.
Accordingly, the adverse influence of the cross-talk noise can be reduced.
It is preferred that the cross-talk noise improving cell is inserted into a first wire by the designing unit in cases where a level transition period of a signal of the first wire overlaps with a level transition period of a signal of a second wire adjacent to the first wire and the level transition period corresponding to the first wire is longer than that corresponding to the second wire.
Accordingly, the adverse influence of the cross-talk noise can be reduced.
It is preferred that a plurality of types of cross-talk noise improving cells are embedded in the internal open space of the hard macro-block by the designing unit, and one type of cross-talk noise improving cell selected from the types of cross-talk noise improving cells is inserted into the wire of the semiconductor integrated circuit by the designing unit.
Accordingly, the adverse influence of the cross-talk noise can be reduced with high precision.
It is preferred that a plurality cross-talk noise improving cells are embedded in the internal open space of the hard macro-block by the designing unit, and one or more cross-talk noise improving cells selected from the cross-talk noise improving cells are inserted into the wire of the semiconductor integrated circuit by the designing unit.
Accordingly, the adverse influence of the cross-talk noise can be reduced with high precision.
It is preferred that the cross-talk noise improving cell is embedded in an open space, which is placed in the outside of the hard macro-block, by the designing unit to insert the cross-talk noise improving cell into the wire of the semiconductor integrated circuit.
Accordingly, the cross-talk noise can be reduced without increasing an area of the semiconductor integrated circuit.
It is preferred that connection information of the cross-talk noise improving cell is output as a netlist by the designing unit.
Accordingly, an operator can ascertain the connection of the cross-talk noise improving cell with the wire.
It is preferred that connection information of the cross-talk noise improving cell is output by the designing unit as a netlist in which the cross-talk noise improving cell embedded in the internal open space of the hard macro-block seems to be arranged independent of the hard macro-block.
Accordingly, an operator can easily ascertain the connection of the cross-talk noise improving cell with the wire.
The object is also achieved by the provision of an automatic cell placement and routing apparatus in which the placement of hard macro-blocks composing a semiconductor integrated circuit is designed and the routing in the semiconductor integrated circuit is designed. An automatic cell placement and routing apparatus comprises a designing unit for placing a signal driving cell at a position near to a cross-coupling occurring position and inserting the signal driving cell into a wire of the semiconductor integrated circuit.
In the above configuration, because the signal driving cell is moved to the position near to the cross-coupling occurring position, a wire length between the signal driving cell and the cross-coupling occurring position is shortened. Therefore, the capacitance between the wire and another adjacent wire corresponding to the occurrence of noise is reduced.
Accordingly, the cross-talk noise can be reduced without increasing an area of the semiconductor integrated circuit.
The object is also achieved by the provision of an automatic cell placement and routing apparatus in which the placement of hard macro-blocks composing a semiconductor integrated circuit is designed and the routing in the semiconductor integrated circuit is designed. An automatic cell placement and routing apparatus comprises a designing unit for moving one of wires, which are adjacent to each other and are arranged in a wiring plane, to another wiring plane and arranging a shielding wire in an opening area in which the moved wire is originally arranged.
In the above configuration, the shielding wire is arranged in place of the moved wire.
Accordingly, the cross-talk noise can be reduced without increasing an area of the semiconductor integrated circ
Hirakimoto Koji
Saito Ken
Umeda Tatsuya
Burns Doane Swecker & Mathis L.L.P.
Kik Phallaka
Renesas Technology Corp.
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