Automatic cache activation and deactivation for power reduction

Details Automatic cache activation and deactivation for power reduction Automatic cache activation and deactivation for power reduction

2007-09-04

2007-09-04

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S118000, C713S320000

Reexamination Certificate

active

11034617

ABSTRACT:
The amount of chip power that is consumed for cache storage size maintenance is optimized by the close monitoring and control of frequency of missed requests, and the proportion of frequently recurring items to all traffic items. The total number of hit slots is measured per interval of time and is compared to the theoretical value based on random distribution. If the missed rate is high, then the observed effect and value of increasing cache size are deduced by observing how this increase affects the distribution of hits on all cache slots. As the number of frequently hit items in proportion to the total traffic items increases, the benefits of increasing the cache size decreases.

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An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches, Se-Hyun Yang et al, Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA), 2001, 11 pp.

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