Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-10-20
2002-03-19
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06360354
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an automatic arrangement of wiring patterns in semiconductor device. More specifically, the present invention is directed to an automatic arrangement of wiring patterns in semiconductor device in high integration while omitting step of confirming interference occurred in wiring patterns inside and outside function blocks.
2. Description of the Related Art
As known in the method of automatically arranging and wiring patterns of semiconductor device, function blocks are called as “hardware-based cores”, or “cores” simply, and these cores are arranged in a semiconductor device such as a gate array. A core is designed by a combination of function cells and a primitive made of a plurality of function cells. In connection with multi-functions of a core, very recently, a total number of terminals of the core is increased. The total number of terminals may mainly influence the size of the core. Function blocks of a semiconductor device are arranged and wired by utilizing a computer.
Referring now to the drawings, a conventional automatic arranging and wiring method of a semiconductor device containing a core (related art 1) will be described.
FIG. 1
is a flow chart for describing the conventional automatic arranging and wiring method as the related art 1.
FIG. 2A
is a plan view for representing setting of a boundary line of a core in accordance with the related art 1 of FIG.
1
.
FIG. 2B
is an enlarged plan view for showing the vicinity of the boundary line (inside circle) of the core indicated in FIG.
2
A. Also,
FIG. 3
is a plan view for representing the core arranging and wiring patterns, corresponding to
FIG. 2A
, formed by the conventional arranging and wiring method as the related art 1.
Referring now to the flow chart of
FIG. 1
, the automatic arranging and wiring method of the related art 1 will be explained.
At a step S
20
, an optimum size of a core is set based upon a circuit scale of the core. As indicated in
FIG. 2A
, a boundary line
12
is set for a region (an automatic layout region) where an automatic layout process is performed to a cell array region
11
.
Next, at a step S
21
, a function cell
18
inside the core is an interface with an external circuit outside the core. The function cell
18
is arranged inside the automatic layout region set at the step S
20
such that the function cell (the interface function cell)
18
is located adjacent to the boundary line
12
.
In this case, this is because the designing flexibility of internal wiring lines (corresponding to wiring lines indicated by reference numeral
17
shown in
FIG. 3
) arranged in the core is increased, when the internal wiring lines are automatically designed by using a computer.
Subsequently, at a step S
22
, the internal wiring lines
17
are automatically arranged and wired by using an automatic arranging and wiring program in which data related to the plurality of interface function cells
18
has been entered. At this time, as indicated in
FIG. 3
, each of the internal wiring lines
17
is connected to the plurality of interface function cells
18
.
Next, at a step S
23
, with reference to the automatic arranging and wiring result of the core formed at the step S
22
, a judgment is made whether or not a wiring line region “K” is reserved between the boundary line
12
and all of the terminals
19
of the interface function cells
18
. In this case, the wiring line region “K” is used to arrange wiring lines (external wiring lines, not shown in detail) connected to external circuits outside the core. In other words, a confirmation is made that any of the internal wiring lines
17
are not present between the terminals
19
and the boundary line
12
.
When it is so judged that the wiring line region K is not reserved between all of the terminals
19
of the interface function cells
18
and the boundary line
12
, the automatic arranging and wiring operation of the core corresponding to the step S
22
is again performed. Otherwise, the automatic arranging and wiring result of the core generated at the step S
22
is manually corrected.
If the result of the judgment at the step S
23
is desired, then the judged automatic arranging and wiring result is outputted as layout data. It should be understood that since, in
FIG. 3
, the wiring region K is reserved between all of the terminals
19
and the boundary line
12
,
FIG. 3
schematically represents this automatic arranging and wiring result judged as a “desired” result at the step S
23
.
As a consequence, the terminals
19
corresponding to the automatic arranging and wiring result outputted as the layout data can be terminals which are directly connectable with the external wiring lines without causing shortcircuits with the internal wiring lines
17
.
However, in the above-described related art 1, in case that the wiring region K near the boundary line
12
cannot be reserved, the automatic arranging and wiring operation must be repeatedly performed. Otherwise, the correcting work is required, resulting in lowering of the design efficiency.
To avoid this problem, another related art about automatic arranging and wiring method has been proposed with using a virtual block as a terminal portion of a core.
This conventional designing method (namely, related art 2) will now be explained with reference to
FIG. 4
to FIG.
7
.
FIG. 4
is a flow chart for describing the conventional automatic arranging and wiring method as the related art 2.
FIG. 5A
is a plan view for representing setting of the boundary line of the core in the related art 2, similar to FIG.
2
A.
FIG. 5B
is an enlarged plan view for showing the vicinity of the boundary line of the core indicated in
FIG. 5A
, similar to FIG.
2
B.
FIG. 6
is a plan view for representing a layout formed by the conventional arranging and wiring method as the related art 2, similar to FIG.
3
.
FIG. 7A
is a schematic circuit diagram for indicating a subject circuit for the conventional automatic arranging and wiring method of FIG.
4
.
FIG. 7B
is a circuit diagram formed by inserting a virtual block into the schematic circuit diagram shown in FIG.
7
A.
As indicated in FIG.
4
and
FIG. 7A
, at a first step S
25
of
FIG. 4
, a position of an external terminal
8
outside a core is predicted, and a virtual block
32
is inserted between this predicted external terminal
8
and a function cell
28
to be an interface of the core. This condition is indicated in FIG.
7
B. In FIG.
7
A and
FIG. 7B
, symbol “H” indicates a group of function cells arranged inside a boundary line
12
of the core except for the plurality of function cells
28
.
At a next step S
26
, a position of a terminal
31
of the virtual block
32
is determined.
At a next step S
27
, an optimum size of the core is determined based upon a circuit scale of the core, and the boundary line
12
which marks a region for an automatic layout is set, as shown in FIG.
5
A.
Next, at a step S
28
, the virtual block
32
shown in
FIG. 5B
is arranged adjacent to the boundary line
12
of the core. In this case, a size of this virtual block
32
is defined based upon a single cell of a minimum unit cell (corresponding to a minimum rectangular shape surrounded by a broken line in
FIG. 5B
) in the core. The terminal
31
of the virtual block
32
is set within the virtual block
32
.
At a next step S
29
, an operation of automatically arranging and wiring internal wiring lines
17
of the core is performed by utilizing an automatic arranging and wiring program in which the condition defined at the step S
28
is entered.
At a further step S
30
, the automatic arranging and wiring result of the core formed at the step S
29
is outputted as layout data of the core shown in FIG.
6
. As a consequence, the terminal
31
connected to the internal wiring line
17
becomes a terminal to be an interface of the core.
Different from the first-mentioned related art 1, the second related art 2 has the following merits. The region where no virt
Do Thuan
NEC Corporation
Scully Scott Murphy & Presser
Smith Matthew
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