Automatic and transparent hardware conversion of traditional...

Details Automatic and transparent hardware conversion of traditional... Automatic and transparent hardware conversion of traditional...

2006-08-31

2008-08-05

Li, Aimee J (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Instruction modification based on condition

Reexamination Certificate

active

07409534

ABSTRACT:
A computing device that provides hardware conversion of flow control predicates associated with program instructions executable within the computing device, detects the beginning and the end of a branch domain of the program instructions, and realizes the beginning and the end of the branch domain at execution time, for selectively enabling and disabling instructions within said branch domain.

REFERENCES:
patent: 6029228 (2000-02-01), Cai et al.
patent: 6041399 (2000-03-01), Terada et al.
patent: 6334184 (2001-12-01), Dhong et al.
patent: 6662294 (2003-12-01), Kahle et al.
patent: 6757816 (2004-06-01), Yoaz et al.
Klauser et al., Dynamic Hammock Predication for Non-Predicated Instruction Set Architectures, Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Oct. 1998.
Klauser et al., Dynamic Hammock Predication for Non-Predicated Instruction Set Architectures, Proceedings of the 1998 International Conferenceon Parallel Architectures and Compilation Techniques, Oct. 1998. cited by examiner.
http://www.websters-online-dictionary.org/ search term: backward compatible. cited by examiner, 1998.
http://www.webopedia.com/ search term: backward compatible. cited by examiner. 2001.
http://foldoc.org/ search term: backward compatible. cited by examiner, 2003.
Microsoft Press.RTM.. “Computer Dictionary: The Comprehensive Standard for Business, School, Library, and Home”. Second Edition. Redmond, Washington: Microsoft Press, .COPYRGT. 1994. p. 133. cited by examiner.
Agerwala et al., “Data Flow Systems—Special Issue,” IEEE Computer, vol. 15, No. 2, pp. 10-13, 1982. cited by other.
Aiken et al., “Perfect Pipelining: A New Loop Parallelization Technique,” in Proceedings of the 1988 European Symposium on Programming, 1988, 15 pages total. cited by other.
Austin et al., “Dynamic Dependency Analysis of Ordinary Programs,” in Proceedings of the 19th Annual International Symposium on Computer Architecture, Gold Coast, Australia, pp. 342-351, IEEE and ACM, May 1992. cited by other.
Banerjee et al., “Fast Execution of Loops With IF Statements,” IEEE Transactions on Computers, vol. C-33, pp. 1030-1033, Nov. 1984. cited by other.
Beck et al., “The cydra 5 minisupercomputer: Architecture and implementation,” Journal of Supercomputing, vol. 7, pp. 143-180, 1993. cited by other.
Breckelbaum et al., “Hierarchical Scheduling Windows,” in Proceedings of the 35th Annual International Symposium on Microarchitecture. Istanbul, Turkey: IEEE, ACM, Nov. 2002. cited by other.
Burger et al., “Billion-Transistor Architectures,” IEEE Computer, vol. 30, No. 9, Sep. 1997. cited by other.
Burger et al., “The SimpleScalar Tool Set, Version 2,” URL: http://www.simplescalar.com/docs/usersguide.sub.—v2.pdf, created 1997, accessed: Jun. 14, 2002. cited by other.
Calder et al., “Value profiling,” in Proceedings of the 30th IEEE Symposium on Microarchitecture, Dec. 1997. cited by other.
Chen, “Supporting Highly Speculative Execution via Adaptive Branch Trees,” in Proceedings of the 4th Annual International Symposium on High Peiformance Computer Architecture: IEEE, Jan. 1998, pp. 185-194. cited by other.
Cleary et al., “Scaling the reorder buffer to 10,000 instructions,” in IEEE TCCA News, pp. 16-20, Jun. 2000. cited by other.
Cleary et al., “The Architecture or an Optimistic CPU: The Warp Engine,” in Proceedings of the HICSS'95, pp. 163-172, University of Hawaii, Jan. 1995. cited by other.
Colwell et al., “A VLIW Architecture For A Trace Scheduling Compiler,” IEEE Transaction on Computers, vol. C-37, pp. 967-979, Aug. 1988. cited by other.
Colwell et al., “A VLIW Architecture for a Trace Scheduling Compiler,” in Proceedings of the Second International Conference Architectural Support for Programming Languages and Operating Systems (ASP LOS II): ACM and IEEE, Sep. 1987, pp. 180-192.cited by other.
Cragon, Branch Strategy Taxonomy and Performance Models, Los Alamitos, California: IEEE Computer Society Press, 1992, 9 pages total. cited by other.
Cytron, “Doacross: Beyond Vectorization for Multiprocessors (Extended Abstract),” in Proceedings of the 1986 International Conference on Parallel Processing, pp. 836-844, Pennsylvania State University and the IEEE Computer Society, Aug. 1986. citedby other.
Dutta et al., “Control Flow Prediction with Tree-Like Subgraphs for Superscalar Processors,” in Proceedings of the 28th International Symposiumon Micmarchitecture (MICRO-28), pp. 258-263, IEEE and ACM, Nov./Dec. 1995. cited by other.
Ebcioglu et al., “DAISY: Dynamic Compilation for 100% Architectural Compatibility,” IBM Research Report RC 20538, IBM Research Division, Aug. 5, 1996, 82 pages total. cited by other.
Ebcioglu, “A Compilation Technique for Software Pipelining of Loops with Conditional Jumps,” in Proceedings of the Twentieth Annual Workshop on Microprogramming (MICRO20), pp. 69-79, Association of Computing Machinery, Dec. 1987. cited by other.
Ellis, Bulldog: A Compliler for VLIW Architectures. PhD thesis, Yale University, New Haven, CT, 292 total pages, 1985. cited by other.
Foster et al., “Percolation of Code to Enhance Parallel Dispatching and Execution,” IEEE Transactions on Computers, vol. C-21, pp. 1411-1415, Dec. 1972. cited by other.
Franklin et al., “Register Traffic Analysis for Streamlining Inter-Operation Communication in Fine-Grain Parallel Processors,” in Proceedings of the Twenty-Fifth International Symposium in Microarchitecture (MICRO-25): IEEE and ACM, Dec. 1992, pp. 236-245. cited by other.
Franklin et al., “The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism,” in Proceedings of the 19th International Syposium on Computer Architecture, pp. 58-67, ACM, May 1992. cited by other.
Ginosar et al., “Adaptive Synchronization,” in Proceedings of the 1998 International Conference on Computer Design, 2 pages total, 1998. cited by other.
Glass, “Crusoe: Transmeta comes out of the closet,” in http://www.linuxplanet.com/linuxplanet/reports/1441/1/, 6 pages total, 2000. cited by other.
Gonzalez et al., “Limits on Instruction-Level Parallelism with Data Speculation,” Department Architectura de Computadores, Universitat Polytechnica Catalan, Barcelona, Spain, Technical Report UPC-DAC-1997-34, 14 pages total, 1997. cited by other.
Gopal et al., “Speculative Versioning Cache,” University of Wisconsin, Madison, Technical Report TR-1334, 11 pages total, Jul. 1997. cited by other.
Gurd et al., “The manchester prototype dataflow computer,” Communications of the ACM, vol. 28, pp. 34-52, Jan. 1985. cited by other.
Henning, “SPEC CPU2000: Measuring CPU Performance in the New Millenium,” IEEE Computer, vol. 33, No. 7, pp. 28-35, Jul. 2000. cited by other.
Henry et al., “Circuits for Wide-Window Superscalar Processors,” in Proceedings of the 27th Annual International Symposium on Computer Architecture. Vancouver, BC, Canada: IEEE and ACM, Jun. 10-14, 2000, pp. 236-247. cited by other.
Henry et al., “The Ultrascalar Processor: An Asymptotically Scalable Superscalar Microarchitecture,” in HIPC '98, Dec. 1998, URL: http://ee.yale.edu/papersIHIPC98-abstract.ps.gz, 18 pages total. cited by other.
Huck et al., “Introducing the ia-64 architecture,” in IEEE Micro, pp. 12-23, Sep. 2000. cited by other.
Jefferson, “Virtual time,” Transactions on Programming Languages and Systems, vol. 7, No. 3, pp. 404-425, Jul. 1985. cited by other.
Jouppi et al., “Available instruction-level parallelism for superscalar and superpipelined machines,” in Proceedings of the International Conference on Architectural Suport for Programming Languages and Operating Systems, pp. 272-282, Apr. 1989.cited by other.
Karkhanis

Affiliated with

Also associated with

Rating

Automatic and transparent hardware conversion of traditional... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automatic and transparent hardware conversion of traditional..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic and transparent hardware conversion of traditional... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4017970