Automatic alignment of integrated circuit and design layout...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10793956

ABSTRACT:
A method, computer program product and system for assessing the impact of anomalies in a physical device. An anomaly may be detected in an integrated circuit. Upon detecting an anomaly, an image of the anomaly may be captured. A design layout of the image may be obtained. The image coordinates of the detected anomaly may be transformed into a common reference system, such as the design layout. By using a common unit of reference instead of different reference systems, automatic coordination of the integrated circuit and the design layout may have to be performed once instead of multiple times for multiple tools. The image coordinates of the detected anomaly may be transformed to the coordinates of a common reference system by vectorizing the image, matching polygons in both the image and the design layout and aligning the image of the anomaly with the design layout of the image.

REFERENCES:
patent: 4954968 (1990-09-01), Yamaguchi et al.
patent: 5401972 (1995-03-01), Talbot et al.
patent: 5541411 (1996-07-01), Lindquist et al.
patent: 5838595 (1998-11-01), Sullivan et al.
patent: 6028664 (2000-02-01), Cheng et al.
patent: 6262430 (2001-07-01), Li
patent: 6330053 (2001-12-01), Takayama
patent: 6804394 (2004-10-01), Hsu
patent: 2004/0202355 (2004-10-01), Hillhouse
Kenneth W. Tobin et al. “Integrated applications of inspection data in the semiconductor manufacturing environment,” Oak Ridge National Laboratory, Oak Ridge, Tennessee, International SEMATECH, Austin, Texas, Dec. 14, 2000, 10 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Automatic alignment of integrated circuit and design layout... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automatic alignment of integrated circuit and design layout..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic alignment of integrated circuit and design layout... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3801655

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.