Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-17
2006-10-17
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C257S775000
Reexamination Certificate
active
07124389
ABSTRACT:
An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.
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Hashimoto Koji
Igarashi Mutsunori
Ikeuchi Atsuhiko
Takashima Makoto
Yamada Masaaki
DLA Piper (US) LLP
Garbowski Leigh M.
Kabushiki Kaisha Toshiba
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