Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-03
2003-12-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C703S013000, C703S014000, C703S015000, C703S016000, C703S017000
Reexamination Certificate
active
06658633
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of testing computer system designs by software simulation; more specifically, it relates to an automated system for system-on-chip (SOC) design verification.
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related by common inventorship and subject matter to co-pending applications titled “Method of Controlling External Models in System-On-Chip Verification” Ser. No. 09/494,230, “Simulator-Independent System-On-Chip Verification Methodology” Ser. No. 09/494,565, “Method of Developing Re-Usable Software for Efficient Verification of System-On-Chip Integrated Circuit Designs” Ser. No. 09/494,907, “Method for Efficient Verification of System-On-Chip Integrated Circuit Designs Including an Embedded Processor” Ser. No. 09/494,564, “Processor-Independent System-On-Chip Verification for Embedded Processor Systems” Ser. No. 09/494,386, and “Method for Re-Using System-On-Chip Verification Software in an Operating System” Ser. No. 09/495,236. The listed applications are assigned to International Business Machines Corporation and are entirely incorporated herein by this reference.
BACKGROUND OF THE INVENTION
The complexity and sophistication of present-day integrated circuit (IC) chips have advanced significantly over those of early chip designs. Where formerly a chip might embody relatively simple electronic logic blocks effected by interconnections between logic gates, currently chips can include combinations of complex, modularized IC designs often called “cores” which together constitute an entire SOC.
In general, IC chip development includes a design phase and a verification phase for determining whether a design works as expected. The verification phase has moved increasingly toward a software simulation approach to avoid the costs of first implementing designs in hardware to verify them.
A key factor for developers and marketers of IC chips in being competitive in business is time-to-market of new products; the shorter the time-to-market, the better the prospects for sales. Time-to-market in turn depends to a significant extent on the duration of the verification phase for new products to be released.
As chip designs have become more complex, shortcomings in existing chip verification methodologies which extend time-to-market have become evident.
Typically, in verifying a design, a simulator is used. Here, “simulator” refers to specialized software whose functions include accepting software written in a hardware description language (HDL) such as Verilog or VHDL which models a circuit design (for example, a core as described above), and using the model to simulate the response of the design to stimuli which are applied by a test case to determine whether the design functions as expected. The results are observed and used to de-bug the design.
In order to achieve acceptably bug-free designs, verification software must be developed for applying a number of test cases sufficient to fully exercise the design in simulation. In the case of SOC designs, the functioning of both the individual cores as they are developed, and of the cores functioning concurrently when interconnected as a system must be verified. Moreover, a complete SOC design usually includes an embedded processor core; simulation which includes a processor core tends to require an inordinate amount of time and computing resources, largely because the processor is usually the most complex piece of circuitry on the chip and interacts with many other cores.
It can be appreciated from the foregoing that verification of an SOC can severely impact time-to-market, due to the necessity of developing and executing software for performing the numerous test cases required to fully exercise the design.
However, inefficiencies in current verification methodologies exacerbate time pressures. For example, design specific verification software must be written or the existing software modified for each specific chip design to be verified.
A verification methodology is needed which will reduce the amount of chip specific design verification software required as well as reduce the time to collect and integrate that software.
SUMMARY OF THE INVENTION
A first aspect of the present invention is a method of verifying the design of an integrated circuit chip comprised of one or more cores, comprising: creating a project core catalog comprising driver description files and application description files for each core; creating a system definition file for the integrated circuit chip; inputting the driver description files, the application description files and the system definition files into a code generator, the code generator outputting a test operating system test code; and applying the test operating system test code to a software simulation of the integrated circuit chip to perform design verification.
A second aspect of the present invention is a program storage device readable by machine, tangibly embodying a program of instructions executable by the machine to perform method steps for verifying the design of an integrated circuit chip comprised of one or more cores the method steps comprising: creating a project core catalog comprising driver description files and application description files for each core; creating a system definition file for the integrated circuit chip; inputting the driver description files, the application description files and the system definition files into a code generator, the code generator outputting a test operating system test code; and applying the test operating system test code to a software simulation of the integrated circuit chip to perform design verification.
A third aspect of the present invention is a computer system comprising a processor, an address/data bus coupled to the processor, and a computer-readable memory unit coupled to communicate with the processor, the memory unit containing instructions that when executed implement a method for verifying the design of an integrated circuit chip comprised of one or more cores, the method comprising the computer implemented steps of: creating a project core catalog comprising driver description files and application description files for each core; creating a system definition file for the integrated circuit chip; inputting the driver description files, the application description files and the system definition files into a code generator, the code generator outputting a test operating system test code; and applying the test operating system test code to a software simulation of the integrated circuit chip to perform design verification.
REFERENCES:
patent: 6427224 (2002-07-01), Devins et al.
patent: 6456961 (2002-09-01), Patil et al.
Chauhan et al., “Verifying IP-Core based System-On-Chip Designs”, IEEE, 1999, pp. 27-31.*
Rincon et al., “Core Design and System-on-a Chip Integration”, IEEE, 1997, pp. 26-35.
Devins Robert J.
Robinson James R.
Kotulak Richard M.
Rossoshek Helen
Schmeiser Olsen & Watts
Siek Vuthe
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