Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-19
2003-01-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06510545
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the shielding of circuits in order to reduce capacitive coupling. More particularly, the present invention relates to an algorithm and CAD tool which designs and generates a shield grid of wires on the power and ground nets of circuits. Shielding is particularly appropriate for dynamic circuits due to their low switching threshold.
2. The Background Art
Dynamic circuits have become necessary for designing high speed and compact circuits, as seen by their use in microprocessors. A domino circuit is a specific type of dynamic circuit wherein the value or logic state is typically held by a capacitor or a weak keeper. One of the main reasons domino circuits are so fast is their low switching threshold. For this same reason, domino circuits also have lower noise margins than static CMOS circuits. In state-of-the-art processes, capacitive coupling on victim wires can push a low signal well above 50% of VDD and cause even static circuits to fail. Capacitive coupling is recognized as one of the most significant contributors of noise to circuits that effect delay and functionality. Other forms of noise, like ground bounce, are much harder to reduce, and have to be tolerated by domino gates. One approach to designing robust dynamic blocks is with wire shielding to nullify aggressor capacitive coupling. A tool and methodology have been developed to implement wire shielding.
A low switching threshold gives dynamic circuits their high speed, but also leads to adverse side effects. A typical domino OR
2
gate (also known as a “2 input OR gate) is shown in FIG.
1
. The reason dynamic gates are fast is the same reason for their lower noise margin, and hence their greater susceptibility to noise than static CMOS. As a consequence, noise is a significant problem since dynamic logic is often employed. Noise comes in the form of charge sharing, charge loss due to capacitive coupling on inputs, IR drop on power wires, leakage and ground bounce. Charge sharing can be prevented by using extra precharge devices to precharge internal nodes. Leakage is controlled with a keeper.
Voltage noise at the inputs of domino gates can cause charge loss at the outn node fairly easily, as shown in FIG.
2
. When X switches high, it causes a glitch on node A through the capacitance between the wires,
10
and
20
, C
c
.,
30
. The capacitance C
c
.,
30
is noise created capacitance. The size of the glitch and the mount of charge loss depends on: the value of C
c
; the slew rate of X; the resistance of the wire from the driver of A to where the glitch occurs, V
tn
(nMos voltage threshhold) and the wire capacitance to ground C
g
. The charge loss is exacerbated when there are two aggressor wire neighbors to A, and when more than one gate input has coupling noise. The charge loss at the outn node can easily lead to functional failure and cause out to switch high with multiple glitches on the same or other inputs.
Although the use of a keeper helps a domino gate recover from charge loss, it is usually too small to prevent the charge loss. Capacitive coupling to the outn or outgoing node of domino gates can be prevented by shielding the node with VDD or VSS wires. As process technology scales, wire dimensions become narrower,
50
and taller
55
, as shown in FIG.
3
. This reduces C
g
and increases C
c
, which makes capacitive coupling from an aggressive neighbor worse and reduces the non-aggressor coupling to a DC wire, C
g
. The metal above,
60
and the metal below
65
are assumed to be at VSS.
Several methods are available for reducing charge loss due to capacitive coupling. These include increasing wire spacing, increasing wire width, adding VDD and VSS shields between wires, as shown in
FIG. 4
, increasing victim driver strength, and reducing aggressor driver strength.
Voltage noises in the form of ground bounce can also cause charge loss. This occurs when ground bounce brings VSS above 0V at the input driver or below 0V at the domino gate receiver, as shown in FIG.
5
. Another form of voltage noise is IR drop on signal wires and the VSS wire distribution grid. Because of the voltage drop across a wire, a low input may not be at 0V if V
1
is greater than V
2
, as shown in FIG.
5
. Ground bounce and IR drop can be reduced by using more pads/bumps for VDD and VSS, wider VDD and VSS wires, shorter signal wires using repeaters, and better substrate taps and guard rings.
SUMMARY OF THE INVENTION
The invention is a shielding method to reduce capacitively and inductively coupled noises on inputs to dynamic gates and other types of circuits from adjacent wires. The invention minimizes the amount of capacitively coupled noise, ensuring predictable timing of signals along paths and allowing full completion of signal routing with short design time. This is accomplished by inserting VDD and VSS wires on both sides of signal wires on the same layer. A systematic shielding strategy is also disclosed.
REFERENCES:
patent: 5491301 (1996-02-01), Akiba et al.
patent: 5499445 (1996-03-01), Boyle et al.
patent: 5761080 (1998-06-01), DeCamp et al.
patent: 5825661 (1998-10-01), Drumm
patent: 5850348 (1998-12-01), Berman
patent: 5867396 (1999-02-01), Parlour
patent: 5910730 (1999-06-01), Sigal
patent: 2261991 (1993-06-01), None
Christopherson Ronald T.
Yee Gin S.
Levin Naum
Siek Vuthe
Sierra Patent Group Ltd.
Sun Microsystems Inc.
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