Automated scan testing of DDR SDRAM

Details Automated scan testing of DDR SDRAM Automated scan testing of DDR SDRAM

2011-06-28

2011-06-28

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07971111

ABSTRACT:
A controller for scan testing a memory. The controller includes a control state machine for controlling the scan process, a test sequence stored in a random access memory used by the control state machine for controlling an actual memory test, a pattern generation data unit responsive to the control state machine for generating a test pattern that is written to and read from a memory under test, a configuration register read by the control state machine for configuring the controller and a fault location register written to by the control state machine for storing locations of defects in the memory. The controller is used to auto scan a memory in real time, interleaved with other processes accessing the memory. The controller has several modes of operation including operating in a periodic burst mode to conserve power and in a background mode so as not to interfere with other processes accessing the scanned memory.

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