Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-10-26
2002-08-13
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06434731
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to the design of integrated circuits and more particularly, relates to the automated placement of a clock distribution network during the design of an integrated circuit.
BACKGROUND OF THE INVENTION
The term chip or integrated circuit as used herein is understood to be thousands to millions of transistors manufactured on a semiconductor substrate and wired together to perform a specific function. The wiring may be aluminum or copper or other conductive material. The number of transistors on a chip, the speed of each transistor, and the delay passing electricity through each transistor and each metal interconnect determine how fast the entire chip operates. The transistors may be configured into logic gates, RAM and/or ROM memory, I/O latches and circuits which input and output signals to and from the chip. Integrated circuits can be categorized into two broad classes: (1) custom circuits; and (2) application specific integrated circuits (ASICs). Custom integrated circuits are uniquely characterized and frequently require manual effort and much time to physically design the circuit. An example of a custom chip is a microprocessor circuit. Designing an ASIC, on the other hand, requires less time using existing technologies and circuits because the circuit is more straightforward. An example of an ASIC is a memory interface circuit.
During integrated circuit design, design engineers pay particular attention to the structure of the clock distribution network. The clock distribution network is the logical and physical structure which provides the pulse to strictly maintain the correct sequence of events throughout the integrated circuit. Such events include receiving and sending data through I/O circuits, on-chip processing and logical operation, and storage of data in memory. Clock signals are typically distributed from a single clock source to many destinations which may be located far apart within the computer. For several reasons, the clock signals do not arrive at all destinations the same time and the difference in time between the arrival of the clock signal at different destinations is called skew. As computers become faster and faster because their clock frequency increases, skew becomes a substantial percentage of the clock period and may actually limit the speed at which the computer can operate. In a physically larger computer system, moreover, the distance between destinations and the clock distribution circuits can vary dramatically, increasing clock skew.
A typical path for a clock signal includes many electronic components, such as gates, integrated circuit (IC) interconnect metals, and wires. Each of these provides an opportunity for introducing undesired clock skew. The amount of time it takes a signal to travel along a wire is called its electrical length, and it depends upon the physical length, the capacitance, and the resistance of the wire path. All else being equal, a signal takes more time to travel a long path than a short one. If the electrical lengths of all the clock signal paths are not equal, skew is introduced.
The clock distribution network often further includes several levels of fanout gates and amplifiers or drivers. Skew results if there are unequal numbers of gates in separate signal paths or if there are variations in how long it takes a signal to pass through different gates. How long it takes a signal to pass through a gate depends upon several factors including the propagation delay characteristics of the particular type of gate, the number of loads the gate is driving, and the temperature of the gate. Any variation of these parameters between two signal paths will cause skew in the signals. Even if these factors are identical, there may be variations between individual gates of the same type.
Crosstalk from adjacent signals can be another cause of clock skew. For example, if during a transition from one logic state to another, a signal's voltage level is altered by crosstalk, then the point in time when the signal is determined to have switched will be altered, thus introducing skew. Another source of skew is when the logic level is determined by reference to a power supply voltage. For example, if the logic levels are defined as voltages relative to ground, any noise on a logic gate's ground reference will affect the time at which the gate determines an input signal to have switched.
There are reasons to minimize and, if possible, to eliminate skew. First, skew limits the speed at which a computer system can operate. Computer tasks are often performed serially with data passed from one stage of the computer to another on subsequent clock cycles. The time period of the clock must be sufficient for a stage to process the data and propagate it to the next stage. In addition, the clock period must allow for any skew between the clock signals at the various stages. For example, if one stage is clocked late because of skew but the next stage is clocked on time, the data from the first stage may not yet have arrived when the second stage is clocked. The clock period thus must be stretched to accommodate not only the time needed for the first stage to process and propagate the data, but also for skew between the clock signals present at the two stages. On the other hand, clock skew may prevent a system from slowing down when the clock frequency is decreased. A clocked electronic system, moreover, may not function at any frequency because of early mode timing faults caused by clock skew.
Computers are typically designed modularly with circuitry placed on various removable circuit boards or modules. Without consideration of the effects of clock skew in the system, the ability of a board or module to be interchanged from one machine to another is severely constrained or even prohibited. The amount of clock skew on a particular module may be different from that on other modules because the time it takes a signal to propagate through a particular type of logic gate varies from gate to gate and each module may have different types and numbers of gates. A system designed to accommodate skew present on one module may not work with other modules. The result is that some modules may not function in all machines because of clock skew.
There are several techniques to reduce clock skew. The design engineer can attempt to equalize the wire between the clock source and all destinations by distributing the clock signals radially from a clock distribution point physically located near the center of the machine. The designer can also equalize the number of gates and types of gates in all clock signal paths. Clock skew can also be reduced by equalizing the load driven by gates and various signal paths. Because these techniques affect the fundamental layout of the circuits, they can only be performed during the physical layout of the system.
There are also techniques to introduce delay into the clock distribution network that can be performed either or both during the design and during the manufacture or installation of the system. The critical parameter is the difference in delay between the various signal paths, not the actual amount of delay in any given path. Thus, a specific amount of delay is introduced in the faster signal paths to match the electrical length of the slowest signal paths and thus compensate for skew. Delay line tuning involves connecting a clock signal path through a delay line to provide multiple outputs, each corresponding to a different delay amount. The output corresponding to the needed delay is selected at the time of installation by reference to other clock signal paths.
The effectiveness and practicality of these methods varies. Equalizing trace lengths, number of gates, and loading must be done during the initial design phase and, as such, cannot account for design changes or component variations. Equalizing the number of gates in the path and the gate loading may not be possible in all circumstances because of other design constraints of the circuit. A previously equalized c
Brennan Thomas Charles
Gower Kevin Charles
Kolor Daniel John
Kusko Erik Victor
Do Thuan
Ojanen Karuna
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