Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-11-29
2010-10-19
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07818692
ABSTRACT:
A method of improving a circuit design for a very large scale integrated circuit is provided which represents a plurality of semiconductor devices interconnected in a circuit. It is determined whether an edge of a feature of one of the plurality of semiconductor devices in the design can be moved in a first direction by a distance within a permitted range, such that a performance goal and a matching goal for the circuit are served. If so, the edge is moved in the first direction by the distance calculated to best serve the performance goal and the matching goal. The foregoing steps may be repeated for each of the plurality of semiconductor devices. If necessary, the foregoing steps may be repeated until the performance goal and matching goal for the circuit are deemed to be adequately served.
REFERENCES:
patent: 6202193 (2001-03-01), Emura et al.
patent: 7009226 (2006-03-01), Sun
patent: 2007/0028195 (2007-02-01), Chidambarrao et al.
patent: 2007/0283301 (2007-12-01), Karandikar et al.
patent: 2008/0148203 (2008-06-01), Alpert et al.
patent: 1638096 (2010-04-01), None
U.S. Appl. No. 11/278,162, filed Mar. 31, 2006 to Christopher J. Gonzalez, entitled: “Method of Implementing Overlay-Based Modification of VLSI Design Layout”.
Chidambarrao Dureseti
Hibbeler Jason
Williams Richard Q.
Chiang Jack
Dimyan Magid Y
International Business Machines - Corporation
Neff Daryl K.
Schnurmann H. Daniel
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