Automated method for the hierarchical and selective...

Details Automated method for the hierarchical and selective... Automated method for the hierarchical and selective...

2005-02-25

2008-03-11

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07343580

ABSTRACT:
An automated method for inserting dummy surfaces into the various layers of the physical design of a multilayer integrated circuit is implemented by an integrated circuit design system. The integrated circuit is organized in interconnected units containing interconnected blocks composed of interconnected cells. The multilayer integrated circuit design, stored in the design system is implemented layer by layer, through selective insertion of patterns of dummy surfaces. The selective insertion is based on an insertion hierarchy with respect to the hierarchy of the physical design of the integrated circuit, by means of individual implementation of the interconnected blocks and first interconnection routing for said interconnected blocks and individual implementation of the interconnected units and second interconnection routing for said interconnected units. The patterns of dummy surfaces are established selectively in accordance with the methods used for designing the blocks of the integrated circuit. The methods used for designing the interconnected blocks include a standard cell method and a custom cell method.

REFERENCES:
patent: 2003/0229868 (2003-12-01), White et al.
patent: 2006/0168551 (2006-07-01), Mukuno

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